[AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg

See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61125

llvm-svn: 363255

2 files changed, 77 insertions, 27 deletions

diff --git a/llvm/test/MC/AMDGPU/sopk-err.s b/llvm/test/MC/AMDGPU/sopk-err.s
index 31466aa8c26..7d1bd8110b5 100644
--- a/llvm/test/MC/AMDGPU/sopk-err.s
+++ b/llvm/test/MC/AMDGPU/sopk-err.s
@@ -8,11 +8,23 @@
 s_setreg_b32  0x1f803, s2
 // GCN: error: invalid immediate: only 16-bit values are legal
 
+s_setreg_b32  typo(0x40), s2
+// GCN: error: expected absolute expression
+
 s_setreg_b32  hwreg(0x40), s2
 // GCN: error: invalid code of hardware register: only 6-bit values are legal
 
 s_setreg_b32  hwreg(HW_REG_WRONG), s2
-// GCN: error: invalid symbolic name of hardware register
+// GCN: error: expected absolute expression
+
+s_setreg_b32  hwreg(1 2,3), s2
+// GCN: error: expected a comma or a closing parenthesis
+
+s_setreg_b32  hwreg(1,2 3), s2
+// GCN: error: expected a comma
+
+s_setreg_b32  hwreg(1,2,3, s2
+// GCN: error: expected a closing parenthesis
 
 s_setreg_b32  hwreg(3,32,32), s2
 // GCN: error: invalid bit offset: only 5-bit values are legal
@@ -33,57 +45,57 @@ s_cbranch_i_fork s[2:3], 0x6
 // GFX10: error: instruction not supported on this GPU
 
 s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
-// SI-ERR: error: invalid symbolic name of hardware register
-// VI-ERR: error: invalid symbolic name of hardware register
+// SI-ERR: specified hardware register is not supported on this GPU
+// VI-ERR: specified hardware register is not supported on this GPU
 // GFX9:   s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
 // GFX10:  s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
 
 s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER)
-// SI-ERR:   error: invalid symbolic name of hardware register
-// VI-ERR:   error: invalid symbolic name of hardware register
-// GFX9-ERR: error: invalid symbolic name of hardware register
+// SI-ERR:   specified hardware register is not supported on this GPU
+// VI-ERR:   specified hardware register is not supported on this GPU
+// GFX9-ERR: specified hardware register is not supported on this GPU
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
 
 s_cmpk_le_u32 s2, -1
diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s
index e5d854c924e..75ee3110bcc 100644
--- a/llvm/test/MC/AMDGPU/sopk.s
+++ b/llvm/test/MC/AMDGPU/sopk.s
@@ -91,6 +91,10 @@ s_cbranch_i_fork s[2:3], 0x6
 // SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
 // VI9:  s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
 
+//===----------------------------------------------------------------------===//
+// getreg/setreg and hwreg macro
+//===----------------------------------------------------------------------===//
+
 // raw number mapped to known HW register
 s_getreg_b32 s2, 0x6
 // SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
@@ -277,6 +281,40 @@ s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
 // SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
 // VI9:  s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
 
+//===----------------------------------------------------------------------===//
+// expressions and hwreg macro
+//===----------------------------------------------------------------------===//
+
+hwreg=6
+s_getreg_b32 s2, hwreg
+// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
+// VI9:  s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+
+x=5
+s_getreg_b32 s2, x+1
+// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
+// VI9:  s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+
+x=5
+s_getreg_b32 s2, 1+x
+// SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
+// VI9:  s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+
+reg=50
+offset=2
+width=30
+s_getreg_b32 s2, hwreg(reg + 1, offset - 1, width + 1)
+// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
+// VI9:  s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
+
+s_getreg_b32 s2, hwreg(1 + reg, -1 + offset, 1 + width)
+// SICI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x02,0xb9]
+// VI9:  s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
 s_endpgm_ordered_ps_done
 // GFX9:     s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 // NOSICIVI: error: instruction not supported on this GPU