AMDGPU] Assembler: better support for immediate literals in assembler.

Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.

With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
    - We parsed fp literal:
        - Instruction expects 64-bit operand:
            - If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
                - then we do nothing this literal
            - Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
                - report error
            - Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
                - If instruction expect fp operand type (f64)
                    - Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
                        - If so then do nothing
                    - Else (e.g. v_fract_f64 v[0:1], 3.1415)
                        - report warning that low 32 bits will be set to zeroes and precision will be lost
                        - set low 32 bits of literal to zeroes
                - Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
                    - report error as it is unclear how to encode this literal
        - Instruction expects 32-bit operand:
            - Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
            - Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
                - do nothing
                - Else report error
            - Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
    - Parsed binary literal:
        - Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
            - do nothing
        - Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
            - report error
        - Else, literal is not-inlinable and we are not required to inline it
            - Are high 32 bit of literal zeroes or same as sign bit (32 bit)
                - do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
            - Else
                - report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)

For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
    OPERAND_REG_IMM32_INT,
    OPERAND_REG_IMM32_FP,
    OPERAND_REG_INLINE_C_INT,
    OPERAND_REG_INLINE_C_FP,
}
'''

This is not working yet:
    - Several tests are failing
    - Problems with predicate methods for inline immediates
    - LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, artem.tamazov

Differential Revision: https://reviews.llvm.org/D22922

llvm-svn: 281050

9 files changed, 1056 insertions, 168 deletions

diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
new file mode 100644
index 00000000000..a552e6751ba
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -0,0 +1,477 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
+
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
+
+//---------------------------------------------------------------------------//
+// fp literal, expected fp operand
+//---------------------------------------------------------------------------//
+
+// SICI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], 0.5
+
+// SICI: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x68,0x00,0x7e]
+// VI: v_sqrt_f64_e32 v[0:1], -4.0 ; encoding: [0xf7,0x50,0x00,0x7e]
+v_sqrt_f64 v[0:1], -4.0
+
+// SICI: v_log_clamp_f32_e32 v1, 0.5 ; encoding: [0xf0,0x4c,0x02,0x7e]
+// NOVI: error: instruction not supported on this GPU
+v_log_clamp_f32 v1, 0.5
+
+// SICI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0.5 ; encoding: [0xf0,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], 0.5
+
+// SICI: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, 0.5 ; encoding: [0xf0,0x38,0x00,0x7e]
+v_trunc_f32 v0, 0.5
+
+// SICI: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], -1.0 ; encoding: [0xf3,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], -1.0
+
+// SICI: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, -1.0 ; encoding: [0xf3,0x38,0x00,0x7e]
+v_trunc_f32 v0, -1.0
+
+// SICI: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 4.0 ; encoding: [0xf6,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], 4.0
+
+// SICI: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, 4.0 ; encoding: [0xf6,0x38,0x00,0x7e]
+v_trunc_f32 v0, 4.0
+
+// SICI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], 0.0
+
+// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e]
+v_trunc_f32 v0, 0.0
+
+// SICI: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf8,0x3f]
+// VI: v_fract_f64_e32 v[0:1], 0x3ff80000 ; encoding: [0xff,0x64,0x00,0x7e,0x00,0x00,0xf8,0x3f]
+v_fract_f64 v[0:1], 1.5
+
+// SICI: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0xc0,0x3f]
+// VI: v_trunc_f32_e32 v0, 0x3fc00000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x00,0xc0,0x3f]
+v_trunc_f32 v0, 1.5
+
+// SICI: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x7c,0x00,0x7e,0xca,0x21,0x09,0xc0]
+// VI: v_fract_f64_e32 v[0:1], 0xc00921ca ; encoding: [0xff,0x64,0x00,0x7e,0xca,0x21,0x09,0xc0]
+v_fract_f64 v[0:1], -3.1415
+
+// SICI: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x42,0x00,0x7e,0x56,0x0e,0x49,0xc0]
+// VI: v_trunc_f32_e32 v0, 0xc0490e56 ; encoding: [0xff,0x38,0x00,0x7e,0x56,0x0e,0x49,0xc0]
+v_trunc_f32 v0, -3.1415
+
+// SICI: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x7c,0x00,0x7e,0x02,0x2d,0xb5,0x44]
+// VI: v_fract_f64_e32 v[0:1], 0x44b52d02 ; encoding: [0xff,0x64,0x00,0x7e,0x02,0x2d,0xb5,0x44]
+v_fract_f64 v[0:1], 100000000000000000000000.0
+
+// SICI: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x42,0x00,0x7e,0x16,0x68,0xa9,0x65]
+// VI: v_trunc_f32_e32 v0, 0x65a96816 ; encoding: [0xff,0x38,0x00,0x7e,0x16,0x68,0xa9,0x65]
+v_trunc_f32 v0, 100000000000000000000000.0
+
+// SICI: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x7c,0x00,0x7e,0xd0,0x12,0x63,0x41]
+// VI: v_fract_f64_e32 v[0:1], 0x416312d0 ; encoding: [0xff,0x64,0x00,0x7e,0xd0,0x12,0x63,0x41]
+v_fract_f64 v[0:1], 10000000.0
+
+// SICI: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x42,0x00,0x7e,0x80,0x96,0x18,0x4b]
+// VI: v_trunc_f32_e32 v0, 0x4b189680 ; encoding: [0xff,0x38,0x00,0x7e,0x80,0x96,0x18,0x4b]
+v_trunc_f32 v0, 10000000.0
+
+// SICI: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xef,0x47]
+// VI: v_fract_f64_e32 v[0:1], 0x47efffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xef,0x47]
+v_fract_f64 v[0:1], 3.402823e+38
+
+// SICI: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x42,0x00,0x7e,0xfd,0xff,0x7f,0x7f]
+// VI: v_trunc_f32_e32 v0, 0x7f7ffffd ; encoding: [0xff,0x38,0x00,0x7e,0xfd,0xff,0x7f,0x7f]
+v_trunc_f32 v0, 3.402823e+38
+
+// SICI: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0x1f,0x38]
+// VI: v_fract_f64_e32 v[0:1], 0x381fffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0x1f,0x38]
+v_fract_f64 v[0:1], 2.3509886e-38
+
+// SICI: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x42,0x00,0x7e,0xff,0xff,0xff,0x00]
+// VI: v_trunc_f32_e32 v0, 0xffffff ; encoding: [0xff,0x38,0x00,0x7e,0xff,0xff,0xff,0x00]
+v_trunc_f32 v0, 2.3509886e-38
+
+// SICI: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x7c,0x00,0x7e,0x23,0xf6,0x79,0x31]
+// VI: v_fract_f64_e32 v[0:1], 0x3179f623 ; encoding: [0xff,0x64,0x00,0x7e,0x23,0xf6,0x79,0x31]
+v_fract_f64 v[0:1], 2.3509886e-70
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_trunc_f32 v0, 2.3509886e-70
+
+//---------------------------------------------------------------------------//
+// fp literal, expected int operand
+//---------------------------------------------------------------------------//
+
+// SICI: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 0.5
+
+// SICI: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0.5, v1
+
+// SICI: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf0,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, 0.5, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf0,0x02,0x02,0x00]
+v_and_b32_e64 v0, 0.5, v1
+
+// SICI: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], -1.0 ; encoding: [0xf3,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], -1.0
+
+// SICI: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, -1.0, v1 ; encoding: [0xf3,0x02,0x00,0x26]
+v_and_b32_e32 v0, -1.0, v1
+
+// SICI: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf3,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, -1.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf3,0x02,0x02,0x00]
+v_and_b32_e64 v0, -1.0, v1
+
+// SICI: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 4.0 ; encoding: [0xf6,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 4.0
+
+// SICI: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, 4.0, v1 ; encoding: [0xf6,0x02,0x00,0x26]
+v_and_b32_e32 v0, 4.0, v1
+
+// SICI: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xf6,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, 4.0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf6,0x02,0x02,0x00]
+v_and_b32_e64 v0, 4.0, v1
+
+// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 0.0
+
+// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0.0, v1
+
+// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00]
+v_and_b32_e64 v0, 0.0, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 1.5
+
+// SICI: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x36,0x00,0x00,0xc0,0x3f]
+// VI: v_and_b32_e32 v0, 0x3fc00000, v1 ; encoding: [0xff,0x02,0x00,0x26,0x00,0x00,0xc0,0x3f]
+v_and_b32_e32 v0, 1.5, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], -3.1415
+
+// SICI: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x36,0x56,0x0e,0x49,0xc0]
+// VI: v_and_b32_e32 v0, 0xc0490e56, v1 ; encoding: [0xff,0x02,0x00,0x26,0x56,0x0e,0x49,0xc0]
+v_and_b32_e32 v0, -3.1415, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 100000000000000000000000.0
+
+// SICI: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x36,0x16,0x68,0xa9,0x65]
+// VI: v_and_b32_e32 v0, 0x65a96816, v1 ; encoding: [0xff,0x02,0x00,0x26,0x16,0x68,0xa9,0x65]
+v_and_b32_e32 v0, 100000000000000000000000.0, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 10000000.0
+
+// SICI: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x36,0x80,0x96,0x18,0x4b]
+// VI: v_and_b32_e32 v0, 0x4b189680, v1 ; encoding: [0xff,0x02,0x00,0x26,0x80,0x96,0x18,0x4b]
+v_and_b32_e32 v0, 10000000.0, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 3.402823e+38
+
+// SICI: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x36,0xfd,0xff,0x7f,0x7f]
+// VI: v_and_b32_e32 v0, 0x7f7ffffd, v1 ; encoding: [0xff,0x02,0x00,0x26,0xfd,0xff,0x7f,0x7f]
+v_and_b32_e32 v0, 3.402823e+38, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 2.3509886e-38
+
+// SICI: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x36,0xff,0xff,0xff,0x00]
+// VI: v_and_b32_e32 v0, 0xffffff, v1 ; encoding: [0xff,0x02,0x00,0x26,0xff,0xff,0xff,0x00]
+v_and_b32_e32 v0, 2.3509886e-38, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 2.3509886e-70
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_and_b32_e32 v0, 2.3509886e-70, v1
+
+//---------------------------------------------------------------------------//
+// int literal, expected fp operand
+//---------------------------------------------------------------------------//
+
+// SICI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, 0 ; encoding: [0x80,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, 0
+
+// SICI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0 ; encoding: [0x80,0x64,0x00,0x7e]
+v_fract_f64_e32 v[0:1], 0
+
+// SICI: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x42,0xd3,0x80,0x00,0x00,0x00]
+// VI: v_trunc_f32_e64 v0, 0 ; encoding: [0x00,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00]
+v_trunc_f32_e64 v0, 0
+
+// SICI: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x7c,0xd3,0x80,0x00,0x00,0x00]
+// VI: v_fract_f64_e64 v[0:1], 0 ; encoding: [0x00,0x00,0x72,0xd1,0x80,0x00,0x00,0x00]
+v_fract_f64_e64 v[0:1], 0
+
+// SICI: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, -13 ; encoding: [0xcd,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, -13
+
+// SICI: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x64,0x00,0x7e]
+v_fract_f64_e32 v[0:1], -13
+
+// SICI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x42,0xd3,0x8d,0x00,0x00,0x20]
+// VI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x5c,0xd1,0x8d,0x00,0x00,0x20]
+v_trunc_f32_e64 v0, -13
+
+// SICI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x7c,0xd3,0x8d,0x00,0x00,0x20]
+// VI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x72,0xd1,0x8d,0x00,0x00,0x20]
+v_fract_f64_e64 v[0:1], -13
+
+// SICI: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, 35
+
+// SICI: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 35 ; encoding: [0xa3,0x64,0x00,0x7e]
+v_fract_f64_e32 v[0:1], 35
+
+// SICI: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x42,0xd3,0xa3,0x00,0x00,0x00]
+// VI: v_trunc_f32_e64 v0, 35 ; encoding: [0x00,0x00,0x5c,0xd1,0xa3,0x00,0x00,0x00]
+v_trunc_f32_e64 v0, 35
+
+// SICI: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x7c,0xd3,0xa3,0x00,0x00,0x00]
+// VI: v_fract_f64_e64 v[0:1], 35 ; encoding: [0x00,0x00,0x72,0xd1,0xa3,0x00,0x00,0x00]
+v_fract_f64_e64 v[0:1], 35
+
+// SICI: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x42,0x00,0x7e,0xd2,0x04,0x00,0x00]
+// VI: v_trunc_f32_e32 v0, 0x4d2 ; encoding: [0xff,0x38,0x00,0x7e,0xd2,0x04,0x00,0x00]
+v_trunc_f32_e32 v0, 1234
+
+// SICI: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x7c,0x00,0x7e,0xd2,0x04,0x00,0x00]
+// VI: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x64,0x00,0x7e,0xd2,0x04,0x00,0x00]
+v_fract_f64_e32 v[0:1], 1234
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_trunc_f32_e64 v0, 1234
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_fract_f64_e64 v[0:1], 1234
+
+// SICI: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff]
+// VI: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x38,0x00,0x7e,0xcf,0x2b,0xff,0xff]
+v_trunc_f32_e32 v0, -54321
+
+// SICI: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x7c,0x00,0x7e,0xcf,0x2b,0xff,0xff]
+// VI: v_fract_f64_e32 v[0:1], 0xffff2bcf ; encoding: [0xff,0x64,0x00,0x7e,0xcf,0x2b,0xff,0xff]
+v_fract_f64_e32 v[0:1], -54321
+
+// SICI: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x42,0x00,0x7e,0xef,0xbe,0xad,0xde]
+// VI: v_trunc_f32_e32 v0, 0xdeadbeef ; encoding: [0xff,0x38,0x00,0x7e,0xef,0xbe,0xad,0xde]
+v_trunc_f32_e32 v0, 0xdeadbeef
+
+// SICI: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x7c,0x00,0x7e,0xef,0xbe,0xad,0xde]
+// VI: v_fract_f64_e32 v[0:1], 0xdeadbeef ; encoding: [0xff,0x64,0x00,0x7e,0xef,0xbe,0xad,0xde]
+v_fract_f64_e32 v[0:1], 0xdeadbeef
+
+// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, 0xffffffff
+
+// SICI: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x7c,0x00,0x7e,0xff,0xff,0xff,0xff]
+// VI: v_fract_f64_e32 v[0:1], 0xffffffff ; encoding: [0xff,0x64,0x00,0x7e,0xff,0xff,0xff,0xff]
+v_fract_f64_e32 v[0:1], 0xffffffff
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_trunc_f32_e32 v0, 0x123456789abcdef0
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_fract_f64_e32 v[0:1], 0x123456789abcdef0
+
+// SICI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x42,0x00,0x7e]
+// VI: v_trunc_f32_e32 v0, -1 ; encoding: [0xc1,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, 0xffffffffffffffff
+
+// SICI: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x7c,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], -1 ; encoding: [0xc1,0x64,0x00,0x7e]
+v_fract_f64_e32 v[0:1], 0xffffffffffffffff
+
+//---------------------------------------------------------------------------//
+// int literal, expected int operand
+//---------------------------------------------------------------------------//
+
+// SICI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 0 ; encoding: [0x80,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 0
+
+// SICI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, 0, v1 ; encoding: [0x80,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0, v1
+
+// SICI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x36,0xd2,0x80,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, 0, v1 ; encoding: [0x00,0x00,0x13,0xd1,0x80,0x02,0x02,0x00]
+v_and_b32_e64 v0, 0, v1
+
+// SICI: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], -13 ; encoding: [0xcd,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], -13
+
+// SICI: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, -13, v1 ; encoding: [0xcd,0x02,0x00,0x26]
+v_and_b32_e32 v0, -13, v1
+
+// SICI: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xcd,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, -13, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xcd,0x02,0x02,0x00]
+v_and_b32_e64 v0, -13, v1
+
+// SICI: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 35 ; encoding: [0xa3,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 35
+
+// SICI: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, 35, v1 ; encoding: [0xa3,0x02,0x00,0x26]
+v_and_b32_e32 v0, 35, v1
+
+// SICI: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x36,0xd2,0xa3,0x02,0x02,0x00]
+// VI: v_and_b32_e64 v0, 35, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xa3,0x02,0x02,0x00]
+v_and_b32_e64 v0, 35, v1
+
+// SICI: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x04,0x80,0xbe,0xd2,0x04,0x00,0x00]
+// VI: s_mov_b64 s[0:1], 0x4d2 ; encoding: [0xff,0x01,0x80,0xbe,0xd2,0x04,0x00,0x00]
+s_mov_b64_e32 s[0:1], 1234
+
+// SICI: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x36,0xd2,0x04,0x00,0x00]
+// VI: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x26,0xd2,0x04,0x00,0x00]
+v_and_b32_e32 v0, 1234, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_and_b32_e64 v0, 1234, v1
+
+// SICI: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x04,0x80,0xbe,0xcf,0x2b,0xff,0xff]
+// VI: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x01,0x80,0xbe,0xcf,0x2b,0xff,0xff]
+s_mov_b64_e32 s[0:1], -54321
+
+// SICI: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x36,0xcf,0x2b,0xff,0xff]
+// VI: v_and_b32_e32 v0, 0xffff2bcf, v1 ; encoding: [0xff,0x02,0x00,0x26,0xcf,0x2b,0xff,0xff]
+v_and_b32_e32 v0, -54321, v1
+
+// SICI: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x04,0x80,0xbe,0xef,0xbe,0xad,0xde]
+// VI: s_mov_b64 s[0:1], 0xdeadbeef ; encoding: [0xff,0x01,0x80,0xbe,0xef,0xbe,0xad,0xde]
+s_mov_b64_e32 s[0:1], 0xdeadbeef
+
+// SICI: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x36,0xef,0xbe,0xad,0xde]
+// VI: v_and_b32_e32 v0, 0xdeadbeef, v1 ; encoding: [0xff,0x02,0x00,0x26,0xef,0xbe,0xad,0xde]
+v_and_b32_e32 v0, 0xdeadbeef, v1
+
+// SICI: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x04,0x80,0xbe,0xff,0xff,0xff,0xff]
+// VI: s_mov_b64 s[0:1], 0xffffffff ; encoding: [0xff,0x01,0x80,0xbe,0xff,0xff,0xff,0xff]
+s_mov_b64_e32 s[0:1], 0xffffffff
+
+// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0xffffffff, v1
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+s_mov_b64_e32 s[0:1], 0x123456789abcdef0
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_and_b32_e32 v0, 0x123456789abcdef0, v1
+
+// SICI: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x04,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], -1 ; encoding: [0xc1,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 0xffffffffffffffff
+
+// SICI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x36]
+// VI: v_and_b32_e32 v0, -1, v1 ; encoding: [0xc1,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0xffffffffffffffff, v1
+
+//---------------------------------------------------------------------------//
+// 1/(2*PI)
+//---------------------------------------------------------------------------//
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_trunc_f32_e32 v0, 0x3fc45f306dc9c882
+
+// NOSICI: error: invalid operand for instruction
+// VI: v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882 ; encoding: [0xf8,0x64,0x00,0x7e]
+v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882
+
+// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
+// VI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xf8,0x38,0x00,0x7e]
+v_trunc_f32_e32 v0, 0x3e22f983
+
+// SICI: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e]
+// VI: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x64,0x00,0x7e,0x83,0xf9,0x22,0x3e]
+v_fract_f64_e32 v[0:1], 0x3e22f983
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_trunc_f32_e64 v0, 0x3fc45f306dc9c882
+
+// NOSICI: error: invalid operand for instruction
+// VI: v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
+v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882
+
+// NOSICI: error: invalid operand for instruction
+// VI: v_trunc_f32_e64 v0, 0x3e22f983 ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00]
+v_trunc_f32_e64 v0, 0x3e22f983
+
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_fract_f64_e64 v[0:1], 0x3e22f983
+
+// NOSICI: error: invalid operand for instruction
+// VI: s_mov_b64 s[0:1], 0x3fc45f306dc9c882 ; encoding: [0xf8,0x01,0x80,0xbe]
+s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335
+
+// SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e]
+// VI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xf8,0x02,0x00,0x26]
+v_and_b32_e32 v0, 0.159154943091895317852646485335, v1
+
+// NOSICI: error: invalid operand for instruction
+// VI: v_and_b32_e64 v0, 0x3e22f983, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00]
+v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
+
+// SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f]
+// VI: v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882 ; encoding: [0xf8,0x64,0x00,0x7e]
+v_fract_f64 v[0:1], 0.159154943091895317852646485335
+
+// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
+// VI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xf8,0x38,0x00,0x7e]
+v_trunc_f32 v0, 0.159154943091895317852646485335
\ No newline at end of file
diff --git a/llvm/test/MC/AMDGPU/reg-syntax-extra.s b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
index 52892a4e5e2..f4a072930e3 100644
--- a/llvm/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/llvm/test/MC/AMDGPU/reg-syntax-extra.s
@@ -43,7 +43,7 @@ s_mov_b64 [tma_lo,tma_hi], s[2:3]
 // SICI:  s_mov_b64 tma, s[2:3]           ; encoding: [0x02,0x04,0xee,0xbe]
 // VI:    s_mov_b64 tma, s[2:3]           ; encoding: [0x02,0x01,0xee,0xbe]
 
-v_mov_b32 [v1], [v2]
+v_mov_b32_e32 [v1], [v2]
 // GCN:  v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
 
 v_rcp_f64 [v1,v2], [v2,v3]
diff --git a/llvm/test/MC/AMDGPU/regression/bug28165.s b/llvm/test/MC/AMDGPU/regression/bug28165.s
new file mode 100644
index 00000000000..c9e3f5b60e4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/regression/bug28165.s
@@ -0,0 +1,11 @@
+// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
+
+// SICI: v_cmp_eq_f64_e32 vcc, 0.5, v[254:255] ; encoding: [0xf0,0xfc,0x45,0x7c]
+// VI: v_cmp_eq_f64_e32 vcc, 0.5, v[254:255] ; encoding: [0xf0,0xfc,0xc5,0x7c]
+v_cmp_eq_f64 vcc, 0.5, v[254:255]
+
+// GCN: v_cvt_f32_f64_e32 v0, 0.5 ; encoding: [0xf0,0x1e,0x00,0x7e]
+v_cvt_f32_f64 v0, 0.5
diff --git a/llvm/test/MC/AMDGPU/regression/bug28413.s b/llvm/test/MC/AMDGPU/regression/bug28413.s
index d5b2ff90cd9..425d996ef60 100644
--- a/llvm/test/MC/AMDGPU/regression/bug28413.s
+++ b/llvm/test/MC/AMDGPU/regression/bug28413.s
@@ -19,10 +19,10 @@ v_cmpx_eq_u32 vcc, 3.125, v0
 // SICI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xa4,0x7d,0x00,0x00,0x48,0x40]
 // VI: v_cmpx_eq_u32_e32 vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0xb4,0x7d,0x00,0x00,0x48,0x40]
 
-v_mov_b32 v0, 0.5
+v_mov_b32_e32 v0, 0.5
 // GCN: v_mov_b32_e32 v0, 0.5 ; encoding: [0xf0,0x02,0x00,0x7e]
 
-v_mov_b32 v0, 3.125
+v_mov_b32_e32 v0, 3.125
 // GCN: v_mov_b32_e32 v0, 0x40480000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x00,0x48,0x40]
 
 v_add_i32 v0, vcc, 0.5, v0
diff --git a/llvm/test/MC/AMDGPU/sop1-err.s b/llvm/test/MC/AMDGPU/sop1-err.s
index 4329451a650..65dbdb98ede 100644
--- a/llvm/test/MC/AMDGPU/sop1-err.s
+++ b/llvm/test/MC/AMDGPU/sop1-err.s
@@ -26,17 +26,6 @@ s_mov_b64 s1, s[0:1]
 s_mov_b64 s[0:1], s1
 // GCN: error: invalid operand for instruction
 
-// Immediate greater than 32-bits
-s_mov_b32 s1, 0xfffffffff
-// GCN: error: invalid immediate: only 32-bit values are legal
-
-// Immediate greater than 32-bits
-s_mov_b64 s[0:1], 0xfffffffff
-// GCN: error: invalid immediate: only 32-bit values are legal
-
-s_mov_b64 s[0:1], 0x0000000200000000
-// GCN: error: invalid immediate: only 32-bit values are legal
-
 // FIXME: This shoudl probably say failed to parse.
 s_mov_b32 s
 // GCN: error: not a valid operand
diff --git a/llvm/test/MC/AMDGPU/trap.s b/llvm/test/MC/AMDGPU/trap.s
index 3695da518ca..52face5f41d 100644
--- a/llvm/test/MC/AMDGPU/trap.s
+++ b/llvm/test/MC/AMDGPU/trap.s
@@ -62,7 +62,7 @@ s_lshr_b32    ttmp8, ttmp8, 12
 // SICI: s_lshr_b32 ttmp8, ttmp8, 12     ; encoding: [0x78,0x8c,0x78,0x90]
 // VI:   s_lshr_b32 ttmp8, ttmp8, 12     ; encoding: [0x78,0x8c,0x78,0x8f]
 
-v_mov_b32     v1, ttmp8
+v_mov_b32_e32     v1, ttmp8
 // SICI: v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
 // VI:   v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
 
diff --git a/llvm/test/MC/AMDGPU/vop1.s b/llvm/test/MC/AMDGPU/vop1.s
index 22a4f91afef..e55c05e5c53 100644
--- a/llvm/test/MC/AMDGPU/vop1.s
+++ b/llvm/test/MC/AMDGPU/vop1.s
@@ -32,71 +32,71 @@ v_clrexcp_e32
 v_nop
 
 // GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
-v_mov_b32 v1, v2
+v_mov_b32_e32 v1, v2
 
 // GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
 v_readfirstlane_b32 s1, v2
 
 // GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
-v_cvt_i32_f64 v1, v[2:3]
+v_cvt_i32_f64_e32 v1, v[2:3]
 
 // GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
-v_cvt_f64_i32 v[1:2], v2
+v_cvt_f64_i32_e32 v[1:2], v2
 
 // GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
-v_cvt_f32_i32 v1, v2
+v_cvt_f32_i32_e32 v1, v2
 
 // GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e]
-v_cvt_f32_u32 v1, v2
+v_cvt_f32_u32_e32 v1, v2
 
 // GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e
-v_cvt_u32_f32 v1, v2
+v_cvt_u32_f32_e32 v1, v2
 
 // GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e]
-v_cvt_i32_f32 v1, v2
+v_cvt_i32_f32_e32 v1, v2
 
 // SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e]
 // NOVI: error: instruction not supported on this GPU
-v_mov_fed_b32 v1, v2
+v_mov_fed_b32_e32 v1, v2
 
 // GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e]
-v_cvt_f16_f32 v1, v2
+v_cvt_f16_f32_e32 v1, v2
 
 // GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e]
-v_cvt_f32_f16 v1, v2
+v_cvt_f32_f16_e32 v1, v2
 
 // GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e]
-v_cvt_rpi_i32_f32 v1, v2
+v_cvt_rpi_i32_f32_e32 v1, v2
 
 // GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
-v_cvt_flr_i32_f32 v1, v2
+v_cvt_flr_i32_f32_e32 v1, v2
 
 // GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
 v_cvt_off_f32_i4_e32 v1, v2
 
 // GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
-v_cvt_f32_f64 v1, v[2:3]
+v_cvt_f32_f64_e32 v1, v[2:3]
 
 // GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
-v_cvt_f64_f32 v[1:2], v2
+v_cvt_f64_f32_e32 v[1:2], v2
 
 // GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
-v_cvt_f32_ubyte0 v1, v2
+v_cvt_f32_ubyte0_e32 v1, v2
 
 // GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
 v_cvt_f32_ubyte1_e32 v1, v2
 
 // GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
-v_cvt_f32_ubyte2 v1, v2
+v_cvt_f32_ubyte2_e32 v1, v2
 
 // GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
-v_cvt_f32_ubyte3 v1, v2
+v_cvt_f32_ubyte3_e32 v1, v2
 
 // GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
-v_cvt_u32_f64 v1, v[2:3]
+v_cvt_u32_f64_e32 v1, v[2:3]
 
 // GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
-v_cvt_f64_u32 v[1:2], v2
+v_cvt_f64_u32_e32 v[1:2], v2
 
 // NOSI: error: instruction not supported on this GPU
 // NOSI: v_trunc_f64_e32 v[1:2], v[2:3]
@@ -219,19 +219,19 @@ v_cos_f32 v1, v2
 
 // SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
 // VI:   v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
-v_not_b32 v1, v2
+v_not_b32_e32 v1, v2
 
 // SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
 // VI:   v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
-v_bfrev_b32 v1, v2
+v_bfrev_b32_e32 v1, v2
 
 // SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
 // VI:   v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
-v_ffbh_u32 v1, v2
+v_ffbh_u32_e32 v1, v2
 
 // SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
 // VI:   v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
-v_ffbl_b32 v1, v2
+v_ffbl_b32_e32 v1, v2
 
 // SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
 // VI:   v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e]
@@ -239,19 +239,19 @@ v_ffbh_i32_e32 v1, v2
 
 // SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
 // VI:   v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
-v_frexp_exp_i32_f64 v1, v[2:3]
+v_frexp_exp_i32_f64_e32 v1, v[2:3]
 
 // SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
-// VI;   v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
-v_frexp_mant_f64 v[1:2], v[2:3]
+// VI:   v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
+v_frexp_mant_f64_e32 v[1:2], v[2:3]
 
 // SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
 // VI:   v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
-v_fract_f64 v[1:2], v[2:3]
+v_fract_f64_e32 v[1:2], v[2:3]
 
 // SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
 // VI:   v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
-v_frexp_exp_i32_f32 v1, v2
+v_frexp_exp_i32_f32_e32 v1, v2
 
 // SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
 // VI:   v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e]
@@ -259,19 +259,19 @@ v_frexp_mant_f32 v1, v2
 
 // SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
 // VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
-v_clrexcp
+v_clrexcp_e32
 
 // SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
 // VI:   v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
-v_movreld_b32 v1, v2
+v_movreld_b32_e32 v1, v2
 
 // SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
 // VI:   v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
-v_movrels_b32 v1, v2
+v_movrels_b32_e32 v1, v2
 
 // SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
 // VI:   v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
-v_movrelsd_b32 v1, v2
+v_movrelsd_b32_e32 v1, v2
 
 // NOSI: error: instruction not supported on this GPU
 // NOSI: v_log_legacy_f32 v1, v2
@@ -286,91 +286,91 @@ v_log_legacy_f32 v1, v2
 v_exp_legacy_f32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_cvt_f16_u16 v1, v2
+// NOSICI: v_cvt_f16_u16_e32 v1, v2
 // VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
-v_cvt_f16_u16 v1, v2
+v_cvt_f16_u16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_cvt_f16_i16 v1, v2
+// NOSICI: v_cvt_f16_i16_e32 v1, v2
 // VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
-v_cvt_f16_i16 v1, v2
+v_cvt_f16_i16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_cvt_u16_f16 v1, v2
+// NOSICI: v_cvt_u16_f16_e32 v1, v2
 // VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
-v_cvt_u16_f16 v1, v2
+v_cvt_u16_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_cvt_i16_f16 v1, v2
+// NOSICI: v_cvt_i16_f16_e32 v1, v2
 // VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e]
-v_cvt_i16_f16 v1, v2
+v_cvt_i16_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_rcp_f16 v1, v2
+// NOSICI: v_rcp_f16_e32 v1, v2
 // VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e]
-v_rcp_f16 v1, v2
+v_rcp_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_sqrt_f16 v1, v2
+// NOSICI: v_sqrt_f16_e32 v1, v2
 // VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e]
-v_sqrt_f16 v1, v2
+v_sqrt_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_rsq_f16 v1, v2
+// NOSICI: v_rsq_f16_e32 v1, v2
 // VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
-v_rsq_f16 v1, v2
+v_rsq_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_log_f16 v1, v2
+// NOSICI: v_log_f16_e32 v1, v2
 // VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
-v_log_f16 v1, v2
+v_log_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_exp_f16 v1, v2
+// NOSICI: v_exp_f16_e32 v1, v2
 // VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e]
-v_exp_f16 v1, v2
+v_exp_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_frexp_mant_f16 v1, v2
+// NOSICI: v_frexp_mant_f16_e32 v1, v2
 // VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
-v_frexp_mant_f16 v1, v2
+v_frexp_mant_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_frexp_exp_i16_f16 v1, v2
+// NOSICI: v_frexp_exp_i16_f16_e32 v1, v2
 // VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
-v_frexp_exp_i16_f16 v1, v2
+v_frexp_exp_i16_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_floor_f16 v1, v2
+// NOSICI: v_floor_f16_e32 v1, v2
 // VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
-v_floor_f16 v1, v2
+v_floor_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_ceil_f16 v1, v2
+// NOSICI: v_ceil_f16_e32 v1, v2
 // VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
-v_ceil_f16 v1, v2
+v_ceil_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_trunc_f16 v1, v2
+// NOSICI: v_trunc_f16_e32 v1, v2
 // VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
-v_trunc_f16 v1, v2
+v_trunc_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_rndne_f16 v1, v2
+// NOSICI: v_rndne_f16_e32 v1, v2
 // VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e]
-v_rndne_f16 v1, v2
+v_rndne_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_fract_f16 v1, v2
+// NOSICI: v_fract_f16_e32 v1, v2
 // VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e]
-v_fract_f16 v1, v2
+v_fract_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_sin_f16 v1, v2
+// NOSICI: v_sin_f16_e32 v1, v2
 // VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
-v_sin_f16 v1, v2
+v_sin_f16_e32 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_cos_f16 v1, v2
+// NOSICI: v_cos_f16_e32 v1, v2
 // VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
-v_cos_f16 v1, v2
+v_cos_f16_e32 v1, v2
diff --git a/llvm/test/MC/AMDGPU/vop2.s b/llvm/test/MC/AMDGPU/vop2.s
index b4a19fee290..3fa11dd8417 100644
--- a/llvm/test/MC/AMDGPU/vop2.s
+++ b/llvm/test/MC/AMDGPU/vop2.s
@@ -48,27 +48,27 @@ v_mul_i32_i24_e64 v1, v2, v3
 
 // src0 inline
 // SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
-v_mul_i32_i24 v1, 3, v3
+v_mul_i32_i24_e32 v1, 3, v3
 
 // src0 negative inline
 // SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
-v_mul_i32_i24 v1, -3, v3
+v_mul_i32_i24_e32 v1, -3, v3
 
 // src1 inline
 // SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
-v_mul_i32_i24 v1, v2, 3
+v_mul_i32_i24_e64 v1, v2, 3
 
 // src1 negative inline
 // SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
-v_mul_i32_i24 v1, v2, -3
+v_mul_i32_i24_e64 v1, v2, -3
 
 // src0 literal
 // SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
-v_mul_i32_i24 v1, 100, v3
+v_mul_i32_i24_e32 v1, 100, v3
 
 // src1 negative literal
 // SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
-v_mul_i32_i24 v1, -100, v3
+v_mul_i32_i24_e32 v1, -100, v3
 
 //===----------------------------------------------------------------------===//
 // Checks for legal operands
@@ -76,31 +76,31 @@ v_mul_i32_i24 v1, -100, v3
 
 // src0 sgpr
 // SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
-v_mul_i32_i24 v1, s2, v3
+v_mul_i32_i24_e32 v1, s2, v3
 
 // src1 sgpr
 // SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
-v_mul_i32_i24 v1, v2, s3
+v_mul_i32_i24_e64 v1, v2, s3
 
 // src0, src1 same sgpr
 // SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
-v_mul_i32_i24 v1, s2, s2
+v_mul_i32_i24_e64 v1, s2, s2
 
 // src0 sgpr, src1 inline
 // SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
-v_mul_i32_i24 v1, s2, 3
+v_mul_i32_i24_e64 v1, s2, 3
 
 // src0 inline src1 sgpr
 // SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
-v_mul_i32_i24 v1, 3, s3
+v_mul_i32_i24_e64 v1, 3, s3
 
 // SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
 // VI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x32]
-v_add_i32 v0, vcc, 0.5, v0
+v_add_i32_e32 v0, vcc, 0.5, v0
 
 // SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
 // VI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x32,0x00,0x00,0x48,0x40]
-v_add_i32 v0, vcc, 3.125, v0
+v_add_i32_e32 v0, vcc, 3.125, v0
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -147,19 +147,19 @@ v_mul_f32 v1, v2, v3
 
 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
 // VI:   v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
-v_mul_i32_i24 v1, v2, v3
+v_mul_i32_i24_e32 v1, v2, v3
 
 // SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
 // VI:   v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
-v_mul_hi_i32_i24 v1, v2, v3
+v_mul_hi_i32_i24_e32 v1, v2, v3
 
 // SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
 // VI:   v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
-v_mul_u32_u24 v1, v2, v3
+v_mul_u32_u24_e32 v1, v2, v3
 
 // SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
 // VI:   v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
-v_mul_hi_u32_u24 v1, v2, v3
+v_mul_hi_u32_u24_e32 v1, v2, v3
 
 // SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
 // NOVI: error: instruction not supported on this GPU
@@ -181,37 +181,37 @@ v_max_f32 v1, v2 v3
 
 // SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
 // VI:   v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
-v_min_i32 v1, v2, v3
+v_min_i32_e32 v1, v2, v3
 
 // SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
 // VI:   v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
-v_max_i32 v1, v2, v3
+v_max_i32_e32 v1, v2, v3
 
 // SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
 // VI:   v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
-v_min_u32 v1, v2, v3
+v_min_u32_e32 v1, v2, v3
 
 // SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
 // VI:   v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
-v_max_u32 v1, v2, v3
+v_max_u32_e32 v1, v2, v3
 
 // SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
 // NOVI: error: instruction not supported on this GPU
-// NOVI: v_lshr_b32 v1, v2, v3
-v_lshr_b32 v1, v2, v3
+// NOVI: v_lshr_b32_e32 v1, v2, v3
+v_lshr_b32_e32 v1, v2, v3
 
 // SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
 // VI:   v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
-v_lshrrev_b32 v1, v2, v3
+v_lshrrev_b32_e32 v1, v2, v3
 
 // SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
 // NOVI: error: instruction not supported on this GPU
-// NOVI: v_ashr_i32 v1, v2, v3
-v_ashr_i32 v1, v2, v3
+// NOVI: v_ashr_i32_e32 v1, v2, v3
+v_ashr_i32_e32 v1, v2, v3
 
 // SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
 // VI:   v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
-v_ashrrev_i32 v1, v2, v3
+v_ashrrev_i32_e32 v1, v2, v3
 
 // SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
 // NOVI: error: instruction not supported on this GPU
@@ -220,51 +220,51 @@ v_lshl_b32_e32 v1, v2, v3
 
 // SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
 // VI:   v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
-v_lshlrev_b32 v1, v2, v3
+v_lshlrev_b32_e32 v1, v2, v3
 
 // SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
 // VI:   v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
-v_and_b32 v1, v2, v3
+v_and_b32_e32 v1, v2, v3
 
 // SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
 // VI:   v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
-v_or_b32 v1, v2, v3
+v_or_b32_e32 v1, v2, v3
 
 // SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
 // VI:   v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
-v_xor_b32 v1, v2, v3
+v_xor_b32_e32 v1, v2, v3
 
-// SICI: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
+// SICI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x3c,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
-v_bfm_b32 v1, v2, v3
+v_bfm_b32_e64 v1, v2, v3
 
 // SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
 // VI:   v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
-v_mac_f32 v1, v2, v3
+v_mac_f32_e32 v1, v2, v3
 
 // SICI: v_madmk_f32_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
 // VI:   v_madmk_f32_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
-v_madmk_f32 v1, v2, 64.0, v3
+v_madmk_f32_e32 v1, v2, 64.0, v3
 
 // SICI: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
 // VI:   v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
-v_madak_f32 v1, v2, v3, 64.0
+v_madak_f32_e32 v1, v2, v3, 64.0
 
-// SICI: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
+// SICI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x44,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
-v_bcnt_u32_b32 v1, v2, v3
+v_bcnt_u32_b32_e64 v1, v2, v3
 
-// SICI: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
+// SICI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x46,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
-v_mbcnt_lo_u32_b32 v1, v2, v3
+v_mbcnt_lo_u32_b32_e64 v1, v2, v3
 
-// SICI: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48]
+// SICI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x48,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
-v_mbcnt_hi_u32_b32 v1, v2, v3
+v_mbcnt_hi_u32_b32_e64 v1, v2, v3
 
 // SICI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
 // VI:   v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
-v_add_i32 v1, vcc, v2, v3
+v_add_i32_e32 v1, vcc, v2, v3
 
 // SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
@@ -387,38 +387,38 @@ v_cvt_pknorm_u16_f32 v1, v2, v3
 // VI:   v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00]
 v_cvt_pkrtz_f16_f32 v1, v2, v3
 
-// SICI: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
+// SICI: v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x60,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
-v_cvt_pk_u16_u32 v1, v2, v3
+v_cvt_pk_u16_u32_e64 v1, v2, v3
 
-// SICI: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
+// SICI: v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x62,0xd2,0x02,0x07,0x02,0x00]
 // VI:   v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
-v_cvt_pk_i16_i32 v1, v2, v3
+v_cvt_pk_i16_i32_e64 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_add_f16 v1, v2, v3
+// NOSICI: v_add_f16_e32 v1, v2, v3
 // VI:     v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
-v_add_f16 v1, v2, v3
+v_add_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_sub_f16 v1, v2, v3
+// NOSICI: v_sub_f16_e32 v1, v2, v3
 // VI:     v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
-v_sub_f16 v1, v2, v3
+v_sub_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_subrev_f16 v1, v2, v3
+// NOSICI: v_subrev_f16_e32 v1, v2, v3
 // VI:     v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
-v_subrev_f16 v1, v2, v3
+v_subrev_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_mul_f16 v1, v2, v3
+// NOSICI: v_mul_f16_e32 v1, v2, v3
 // VI:     v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
-v_mul_f16 v1, v2, v3
+v_mul_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_mac_f16 v1, v2, v3
+// NOSICI: v_mac_f16_e32 v1, v2, v3
 // VI:     v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
-v_mac_f16 v1, v2, v3
+v_mac_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
 // NOSICI: v_madmk_f16 v1, v2, 64.0, v3
@@ -431,71 +431,71 @@ v_madmk_f16 v1, v2, 64.0, v3
 v_madak_f16 v1, v2, v3, 64.0
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_add_u16 v1, v2, v3
+// NOSICI: v_add_u16_e32 v1, v2, v3
 // VI:     v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
-v_add_u16 v1, v2, v3
+v_add_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_sub_u16 v1, v2, v3
+// NOSICI: v_sub_u16_e32 v1, v2, v3
 // VI:     v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
-v_sub_u16 v1, v2, v3
+v_sub_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_subrev_u16 v1, v2, v3
+// NOSICI: v_subrev_u16_e32 v1, v2, v3
 // VI:     v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
-v_subrev_u16 v1, v2, v3
+v_subrev_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_mul_lo_u16 v1, v2, v3
+// NOSICI: v_mul_lo_u16_e32 v1, v2, v3
 // VI:     v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
-v_mul_lo_u16 v1, v2, v3
+v_mul_lo_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_lshlrev_b16 v1, v2, v3
+// NOSICI: v_lshlrev_b16_e32 v1, v2, v3
 // VI:     v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
-v_lshlrev_b16 v1, v2, v3
+v_lshlrev_b16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_lshrrev_b16 v1, v2, v3
+// NOSICI: v_lshrrev_b16_e32 v1, v2, v3
 // VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
-v_lshrrev_b16 v1, v2, v3
+v_lshrrev_b16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_ashrrev_b16 v1, v2, v3
+// NOSICI: v_ashrrev_b16_e32 v1, v2, v3
 // VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
-v_ashrrev_b16 v1, v2, v3
+v_ashrrev_b16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_max_f16 v1, v2, v3
+// NOSICI: v_max_f16_e32 v1, v2, v3
 // VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
-v_max_f16 v1, v2, v3
+v_max_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_min_f16 v1, v2, v3
+// NOSICI: v_min_f16_e32 v1, v2, v3
 // VI:     v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
-v_min_f16 v1, v2, v3
+v_min_f16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_max_u16 v1, v2, v3
+// NOSICI: v_max_u16_e32 v1, v2, v3
 // VI:     v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
-v_max_u16 v1, v2, v3
+v_max_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_max_i16 v1, v2, v3
+// NOSICI: v_max_i16_e32 v1, v2, v3
 // VI:     v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
-v_max_i16 v1, v2, v3
+v_max_i16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_min_u16 v1, v2, v3
+// NOSICI: v_min_u16_e32 v1, v2, v3
 // VI:     v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
-v_min_u16 v1, v2, v3
+v_min_u16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_min_i16 v1, v2, v3
+// NOSICI: v_min_i16_e32 v1, v2, v3
 // VI:     v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
-v_min_i16 v1, v2, v3
+v_min_i16_e32 v1, v2, v3
 
 // NOSICI: error: instruction not supported on this GPU
-// NOSICI: v_ldexp_f16 v1, v2, v3
+// NOSICI: v_ldexp_f16_e32 v1, v2, v3
 // VI:     v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
-v_ldexp_f16 v1, v2, v3
+v_ldexp_f16_e32 v1, v2, v3
diff --git a/llvm/test/MC/AMDGPU/vop3-convert.s b/llvm/test/MC/AMDGPU/vop3-convert.s
new file mode 100644
index 00000000000..08cfa7832a7
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/vop3-convert.s
@@ -0,0 +1,411 @@
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
+
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
+
+v_mov_b32 [v1], [v2]
+// GCN:  v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
+
+v_mov_b32 v0, 0.5
+// GCN: v_mov_b32_e32 v0, 0.5 ; encoding: [0xf0,0x02,0x00,0x7e]
+
+v_mov_b32_e32 v0, 3.125
+// GCN: v_mov_b32_e32 v0, 0x40480000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x00,0x48,0x40]
+
+v_mov_b32     v1, ttmp8
+// SICI: v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
+// VI:   v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
+
+// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
+v_mov_b32 v1, v2
+
+// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
+// VI:   v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e]
+v_not_b32 v1, v2
+
+// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
+// VI:   v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e]
+v_bfrev_b32 v1, v2
+
+// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
+// VI:   v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e]
+v_ffbh_u32 v1, v2
+
+// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
+// VI:   v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e]
+v_ffbl_b32 v1, v2
+
+// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
+// VI:   v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e]
+v_ffbh_i32_e32 v1, v2
+
+// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e]
+// VI:   v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e]
+v_frexp_exp_i32_f64 v1, v[2:3]
+
+// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e]
+// VI;   v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e]
+v_frexp_mant_f64 v[1:2], v[2:3]
+
+// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e]
+// VI:   v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e]
+v_fract_f64 v[1:2], v[2:3]
+
+// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
+// VI:   v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e]
+v_frexp_exp_i32_f32 v1, v2
+
+// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
+// VI:   v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e]
+v_frexp_mant_f32 v1, v2
+
+// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
+// VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
+v_clrexcp
+
+// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
+// VI:   v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
+v_movreld_b32 v1, v2
+
+// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
+// VI:   v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
+v_movrels_b32 v1, v2
+
+// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
+// VI:   v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
+v_movrelsd_b32 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_f16_u16 v1, v2
+// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e]
+v_cvt_f16_u16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_f16_i16 v1, v2
+// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e]
+v_cvt_f16_i16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_u16_f16 v1, v2
+// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e]
+v_cvt_u16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cvt_i16_f16 v1, v2
+// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e]
+v_cvt_i16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rcp_f16 v1, v2
+// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e]
+v_rcp_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sqrt_f16 v1, v2
+// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e]
+v_sqrt_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rsq_f16 v1, v2
+// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e]
+v_rsq_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_log_f16 v1, v2
+// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e]
+v_log_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_exp_f16 v1, v2
+// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e]
+v_exp_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_frexp_mant_f16 v1, v2
+// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
+v_frexp_mant_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_frexp_exp_i16_f16 v1, v2
+// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
+v_frexp_exp_i16_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_floor_f16 v1, v2
+// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
+v_floor_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ceil_f16 v1, v2
+// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
+v_ceil_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_trunc_f16 v1, v2
+// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e]
+v_trunc_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_rndne_f16 v1, v2
+// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e]
+v_rndne_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_fract_f16 v1, v2
+// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e]
+v_fract_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sin_f16 v1, v2
+// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
+v_sin_f16 v1, v2
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_cos_f16 v1, v2
+// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
+v_cos_f16 v1, v2
+
+// src0 inline
+// SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
+v_mul_i32_i24 v1, 3, v3
+
+// src0 negative inline
+// SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
+v_mul_i32_i24 v1, -3, v3
+
+// src1 inline
+// SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
+v_mul_i32_i24 v1, v2, 3
+
+// src1 negative inline
+// SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
+v_mul_i32_i24 v1, v2, -3
+
+// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e]
+v_cvt_flr_i32_f32 v1, v2
+
+// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e]
+v_cvt_off_f32_i4_e32 v1, v2
+
+// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e]
+v_cvt_f32_f64 v1, v[2:3]
+
+// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e]
+v_cvt_f64_f32 v[1:2], v2
+
+// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e]
+v_cvt_f32_ubyte0 v1, v2
+
+// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e]
+v_cvt_f32_ubyte1_e32 v1, v2
+
+// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e]
+v_cvt_f32_ubyte2 v1, v2
+
+// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e]
+v_cvt_f32_ubyte3 v1, v2
+
+// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e]
+v_cvt_u32_f64 v1, v[2:3]
+
+// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e]
+v_cvt_f64_u32 v[1:2], v2
+
+// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
+// VI:   v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
+v_mul_i32_i24 v1, v2, v3
+
+// SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
+// VI:   v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
+v_mul_hi_i32_i24 v1, v2, v3
+
+// SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
+// VI:   v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
+v_mul_u32_u24 v1, v2, v3
+
+// SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
+// VI:   v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
+v_mul_hi_u32_u24 v1, v2, v3
+
+// SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
+// VI:   v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
+v_min_i32 v1, v2, v3
+
+// SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
+// VI:   v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
+v_max_i32 v1, v2, v3
+
+// SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
+// VI:   v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
+v_min_u32 v1, v2, v3
+
+// SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
+// VI:   v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
+v_max_u32 v1, v2, v3
+
+// SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_lshr_b32 v1, v2, v3
+v_lshr_b32 v1, v2, v3
+
+// SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
+// VI:   v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
+v_lshrrev_b32 v1, v2, v3
+
+// SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_ashr_i32 v1, v2, v3
+v_ashr_i32 v1, v2, v3
+
+// SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
+// VI:   v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
+v_ashrrev_i32 v1, v2, v3
+
+// SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
+// NOVI: error: instruction not supported on this GPU
+// NOVI: v_lshl_b32_e32 v1, v2, v3
+v_lshl_b32_e32 v1, v2, v3
+
+// SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
+// VI:   v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
+v_lshlrev_b32 v1, v2, v3
+
+// SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
+// VI:   v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
+v_and_b32 v1, v2, v3
+
+// SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
+// VI:   v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
+v_or_b32 v1, v2, v3
+
+// SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
+// VI:   v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
+v_xor_b32 v1, v2, v3
+
+// SICI: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
+// VI:   v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
+v_bfm_b32 v1, v2, v3
+
+// SICI: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
+// VI:   v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
+v_bcnt_u32_b32 v1, v2, v3
+
+// SICI: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
+// VI:   v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
+v_mbcnt_lo_u32_b32 v1, v2, v3
+
+// SICI: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48]
+// VI:   v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
+v_mbcnt_hi_u32_b32 v1, v2, v3
+
+// SICI: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
+// VI:   v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pk_u16_u32 v1, v2, v3
+
+// SICI: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
+// VI:   v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
+v_cvt_pk_i16_i32 v1, v2, v3
+
+// SICI: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
+// VI:   v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
+v_bfm_b32 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_add_f16 v1, v2, v3
+// VI:     v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
+v_add_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sub_f16 v1, v2, v3
+// VI:     v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
+v_sub_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_subrev_f16 v1, v2, v3
+// VI:     v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
+v_subrev_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mul_f16 v1, v2, v3
+// VI:     v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
+v_mul_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mac_f16 v1, v2, v3
+// VI:     v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
+v_mac_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_add_u16 v1, v2, v3
+// VI:     v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
+v_add_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_sub_u16 v1, v2, v3
+// VI:     v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
+v_sub_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_subrev_u16 v1, v2, v3
+// VI:     v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
+v_subrev_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_mul_lo_u16 v1, v2, v3
+// VI:     v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
+v_mul_lo_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_lshlrev_b16 v1, v2, v3
+// VI:     v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
+v_lshlrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_lshrrev_b16 v1, v2, v3
+// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
+v_lshrrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ashrrev_b16 v1, v2, v3
+// VI:     v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
+v_ashrrev_b16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_f16 v1, v2, v3
+// VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
+v_max_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_f16 v1, v2, v3
+// VI:     v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
+v_min_f16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_u16 v1, v2, v3
+// VI:     v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
+v_max_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_max_i16 v1, v2, v3
+// VI:     v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
+v_max_i16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_u16 v1, v2, v3
+// VI:     v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
+v_min_u16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_min_i16 v1, v2, v3
+// VI:     v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
+v_min_i16 v1, v2, v3
+
+// NOSICI: error: instruction not supported on this GPU
+// NOSICI: v_ldexp_f16 v1, v2, v3
+// VI:     v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
+v_ldexp_f16 v1, v2, v3