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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2013-10-17 11:02:58 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2013-10-17 11:02:58 +0000
commit561badf717089f5c5afe21afc44a96e9bedf9ec3 (patch)
treee9a4bfde75d972dcef35b17aa5dafe41c5131807 /llvm/test/Linker/linknamedmdnode2.ll
parent21a9c93a4d1551474dd65c8da1c8fc3f2848455d (diff)
downloadbcm5719-llvm-561badf717089f5c5afe21afc44a96e9bedf9ec3.tar.gz
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Fix edge condition in DAGCombiner to improve codegen of shift sequences.
When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. llvm-svn: 192883
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