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| author | Evgeniy Stepanov <eugeni.stepanov@gmail.com> | 2014-03-25 13:08:34 +0000 |
|---|---|---|
| committer | Evgeniy Stepanov <eugeni.stepanov@gmail.com> | 2014-03-25 13:08:34 +0000 |
| commit | fc742acc8c71246f81af7a0214ec5d827aa06f24 (patch) | |
| tree | fd04402bd4628cd70af659979593b11d3fbae2ff /llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll | |
| parent | 1611ed88792a200cefafce4c15789c71592c4820 (diff) | |
| download | bcm5719-llvm-fc742acc8c71246f81af7a0214ec5d827aa06f24.tar.gz bcm5719-llvm-fc742acc8c71246f81af7a0214ec5d827aa06f24.zip | |
[msan] More precise instrumentation of select IR.
Some bits of select result may be initialized even if select condition
is not.
https://code.google.com/p/memory-sanitizer/issues/detail?id=50
llvm-svn: 204716
Diffstat (limited to 'llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll')
| -rw-r--r-- | llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll | 48 |
1 files changed, 33 insertions, 15 deletions
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll index 69e5c18465a..624c706c6e9 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -249,13 +249,16 @@ entry: } ; CHECK: @Select -; CHECK: select -; CHECK-NEXT: sext i1 {{.*}} to i32 +; CHECK: select i1 +; CHECK-NEXT: or i32 +; CHECK-NEXT: xor i32 ; CHECK-NEXT: or i32 -; CHECK-NEXT: select +; CHECK-NEXT: select i1 ; CHECK-ORIGINS: select ; CHECK-ORIGINS: select -; CHECK: select +; CHECK-NEXT: select i1 +; CHECK: store i32{{.*}}@__msan_retval_tls +; CHECK-ORIGINS: store i32{{.*}}@__msan_retval_origin_tls ; CHECK: ret i32 @@ -271,19 +274,18 @@ entry: ; CHECK: @SelectVector ; CHECK: select <8 x i1> -; CHECK-NEXT: sext <8 x i1> {{.*}} to <8 x i16> ; CHECK-NEXT: or <8 x i16> -; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8 -; CHECK-ORIGINS: icmp ne i8 {{.*}}, 0 -; CHECK-ORIGINS: bitcast <8 x i1> {{.*}} to i8 -; CHECK-ORIGINS: icmp ne i8 {{.*}}, 0 -; CHECK-ORIGINS: select i1 -; CHECK-ORIGINS: select i1 -; CHECK: select <8 x i1> +; CHECK-NEXT: xor <8 x i16> +; CHECK-NEXT: or <8 x i16> +; CHECK-NEXT: select <8 x i1> +; CHECK-ORIGINS: select +; CHECK-ORIGINS: select +; CHECK-NEXT: select <8 x i1> +; CHECK: store <8 x i16>{{.*}}@__msan_retval_tls +; CHECK-ORIGINS: store i32{{.*}}@__msan_retval_origin_tls ; CHECK: ret <8 x i16> - ; Check that we propagate origin for "select" with scalar condition and vector ; arguments. Select condition shadow is sign-extended to the vector type and ; mixed into the result shadow. @@ -296,9 +298,10 @@ entry: ; CHECK: @SelectVector2 ; CHECK: select i1 -; CHECK: sext i1 {{.*}} to i128 -; CHECK: bitcast i128 {{.*}} to <8 x i16> ; CHECK: or <8 x i16> +; CHECK: xor <8 x i16> +; CHECK: or <8 x i16> +; CHECK: select i1 ; CHECK-ORIGINS: select i1 ; CHECK-ORIGINS: select i1 ; CHECK: select i1 @@ -320,6 +323,21 @@ entry: ; CHECK: ret { i64, i64 } +define { i64*, double } @SelectStruct2(i1 zeroext %x, { i64*, double } %a, { i64*, double } %b) readnone sanitize_memory { +entry: + %c = select i1 %x, { i64*, double } %a, { i64*, double } %b + ret { i64*, double } %c +} + +; CHECK: @SelectStruct2 +; CHECK: select i1 {{.*}}, { i64, i64 } +; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 } +; CHECK-ORIGINS: select i1 +; CHECK-ORIGINS: select i1 +; CHECK-NEXT: select i1 {{.*}}, { i64*, double } +; CHECK: ret { i64*, double } + + define i8* @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { entry: %0 = inttoptr i64 %x to i8* |
