diff options
author | Dale Johannesen <dalej@apple.com> | 2010-08-31 23:43:55 +0000 |
---|---|---|
committer | Dale Johannesen <dalej@apple.com> | 2010-08-31 23:43:55 +0000 |
commit | 52bd0dc3bb7d3e1a30c38d3ec7e5c33e49ff3080 (patch) | |
tree | 97473e16652e72bcc43a42885b2cd6f08a89ca78 /llvm/test/FrontendC | |
parent | 1835c13fc2cb221a230c1560389a8d5c97f6fd83 (diff) | |
download | bcm5719-llvm-52bd0dc3bb7d3e1a30c38d3ec7e5c33e49ff3080.tar.gz bcm5719-llvm-52bd0dc3bb7d3e1a30c38d3ec7e5c33e49ff3080.zip |
Testcase for llvm checkin 112674.
llvm-svn: 112675
Diffstat (limited to 'llvm/test/FrontendC')
-rw-r--r-- | llvm/test/FrontendC/asm-reg-var-local.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/FrontendC/asm-reg-var-local.c b/llvm/test/FrontendC/asm-reg-var-local.c new file mode 100644 index 00000000000..c3b6c4b1b51 --- /dev/null +++ b/llvm/test/FrontendC/asm-reg-var-local.c @@ -0,0 +1,32 @@ +// RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s +// Exercise various use cases for local asm "register variables". +// XFAIL: * +// XTARGET: x86_64 + +int foo() { +// CHECK: %a = alloca i32 + + register int a asm("rsi")=5; +// CHECK: store i32 5, i32* %a, align 4 + + asm volatile("; %0 This asm defines rsi" : "=r"(a)); +// CHECK: %asmtmp = call i32 asm sideeffect "; $0 This asm defines rsi", "={rsi} +// CHECK: store i32 %asmtmp, i32* %a + + a = 42; +// CHECK: store i32 42, i32* %a, align 4 + + asm volatile("; %0 This asm uses rsi" : : "r"(a)); +// CHECK: %1 = load i32* %a, align 4 +// CHECK: call void asm sideeffect "", "{rsi}"(i32 %1) nounwind +// CHECK: %2 = call i32 asm sideeffect "", "={rsi}"() nounwind +// CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 %2) + + return a; +// CHECK: %3 = load i32* %a, align 4 +// CHECK: call void asm sideeffect "", "{rsi}"(i32 %3) nounwind +// CHECK: %4 = call i32 asm sideeffect "", "={rsi}"() nounwind +// CHECK: store i32 %4, i32* %0, align 4 +// CHECK: %5 = load i32* %0, align 4 +// CHECK: store i32 %5, i32* %retval, align 4 +} |