summaryrefslogtreecommitdiffstats
path: root/llvm/test/DebugInfo/X86/live-debug-variables.ll
diff options
context:
space:
mode:
authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-09-19 18:59:08 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-09-19 18:59:08 +0000
commit2d0f20cc043458c945e4959c5b130c07a7f5b8b5 (patch)
tree4c6c2685582012433738444bea2cce36c82c7b04 /llvm/test/DebugInfo/X86/live-debug-variables.ll
parent894c39f770298e8972d3518c9b3531b59c819f56 (diff)
downloadbcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.tar.gz
bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.zip
[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
Diffstat (limited to 'llvm/test/DebugInfo/X86/live-debug-variables.ll')
-rw-r--r--llvm/test/DebugInfo/X86/live-debug-variables.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/DebugInfo/X86/live-debug-variables.ll b/llvm/test/DebugInfo/X86/live-debug-variables.ll
index 5f510e86a84..e746a0d5718 100644
--- a/llvm/test/DebugInfo/X86/live-debug-variables.ll
+++ b/llvm/test/DebugInfo/X86/live-debug-variables.ll
@@ -25,7 +25,7 @@
; CHECK: .debug_loc contents:
; CHECK-NEXT: 0x00000000:
; We currently emit an entry for the function prologue, too, which could be optimized away.
-; CHECK: [0x000000000000001f, 0x000000000000003c): DW_OP_reg3 RBX
+; CHECK: [0x0000000000000018, 0x0000000000000072): DW_OP_reg3 RBX
; We should only have one entry inside the function.
; CHECK-NOT: :
OpenPOWER on IntegriCloud