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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-01 14:53:53 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-09-01 14:53:53 +0000 |
| commit | bd2715475702e6b178e8db2101c8335e305ef787 (patch) | |
| tree | 0b29d29a9d1e49e625bba9112a4d500d093b4ffb /llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll | |
| parent | fbd3de7851b5874c282c34d9077f470c344e3870 (diff) | |
| download | bcm5719-llvm-bd2715475702e6b178e8db2101c8335e305ef787.tar.gz bcm5719-llvm-bd2715475702e6b178e8db2101c8335e305ef787.zip | |
[mips] interAptiv based generic schedule model
This scheduler describes a processor which covers all MIPS ISAs based
around the interAptiv and P5600 timings.
Reviewers: vkalintiris, dsanders
Differential Revision: https://reviews.llvm.org/D23551
llvm-svn: 280374
Diffstat (limited to 'llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll')
| -rw-r--r-- | llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll b/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll index f77d55bf46d..1e516d7b2c1 100644 --- a/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll +++ b/llvm/test/DebugInfo/Mips/dsr-fixed-objects.ll @@ -29,7 +29,7 @@ declare void @foo(i32*) ; ; x -> DW_OP_reg1(51) ; F0: [[LOC]]: Beginning address offset: 0x0000000000000028 -; F0: Ending address offset: 0x0000000000000030 +; F0: Ending address offset: 0x000000000000002c ; F0: Location description: 51 define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 { @@ -65,7 +65,7 @@ entry: ; x -> DW_OP_reg1(51) ; F1: [[LOC]]: Beginning address offset: 0x0000000000000080 -; F1: Ending address offset: 0x0000000000000088 +; F1: Ending address offset: 0x0000000000000084 ; F1: Location description: 51 define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 { |
