[AMDGPU] Switch to the new addr space mapping by default

This requires corresponding clang change.

Differential Revision: https://reviews.llvm.org/D40955

llvm-svn: 324101

4 files changed, 57 insertions, 57 deletions

diff --git a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
index 4e9d26bc0cb..8be11c72bcf 100644
--- a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
+++ b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll
@@ -4,11 +4,11 @@
 ;
 ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
 ;
-; kernel void kernel1(global int *A) {
+; kernel void kernel1(global int  addrspace(5)*A) {
 ;   *A = 11;
 ; }
 ;
-; kernel void kernel2(global int *B) {
+; kernel void kernel2(global int  addrspace(5)*B) {
 ;   *B = 12;
 ; }
 
@@ -20,20 +20,20 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
 
 define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
 entry:
-  %A.addr = alloca i32 addrspace(1)*, align 4
-  store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !16, metadata !17), !dbg !18
-  %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !19
+  %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
   store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
   ret void, !dbg !21
 }
 
 define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
 entry:
-  %B.addr = alloca i32 addrspace(1)*, align 4
-  store i32 addrspace(1)* %B, i32 addrspace(1)** %B.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %B.addr, metadata !23, metadata !17), !dbg !24
-  %0 = load i32 addrspace(1)*, i32 addrspace(1)** %B.addr, align 4, !dbg !25
+  %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
   store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
   ret void, !dbg !27
 }
@@ -57,7 +57,7 @@ entry:
 !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
 !12 = !{i32 1}
 !13 = !{!"none"}
-!14 = !{!"int*"}
+!14 = !{!"int addrspace(5)*"}
 !15 = !{!""}
 !16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10)
 !17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)
diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
index 19ca08ac781..bc8548f953c 100644
--- a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
+++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll
@@ -4,11 +4,11 @@
 ;
 ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
 ;
-; kernel void kernel1(global int *A) {
+; kernel void kernel1(global int  addrspace(5)*A) {
 ;   *A = 11;
 ; }
 ;
-; kernel void kernel2(global int *B) {
+; kernel void kernel2(global int  addrspace(5)*B) {
 ;   *B = 12;
 ; }
 
@@ -19,20 +19,20 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
 
 define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
 entry:
-  %A.addr = alloca i32 addrspace(1)*, align 4
-  store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !16, metadata !17), !dbg !18
-  %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !19
+  %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
   store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
   ret void, !dbg !21
 }
 
 define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
 entry:
-  %B.addr = alloca i32 addrspace(1)*, align 4
-  store i32 addrspace(1)* %B, i32 addrspace(1)** %B.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %B.addr, metadata !23, metadata !17), !dbg !24
-  %0 = load i32 addrspace(1)*, i32 addrspace(1)** %B.addr, align 4, !dbg !25
+  %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
   store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
   ret void, !dbg !27
 }
@@ -56,7 +56,7 @@ entry:
 !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
 !12 = !{i32 1}
 !13 = !{!"none"}
-!14 = !{!"int*"}
+!14 = !{!"int addrspace(5)*"}
 !15 = !{!""}
 !16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10)
 !17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)
diff --git a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
index 2cb0b018371..6a3dfc5a8e4 100644
--- a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
+++ b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll
@@ -5,11 +5,11 @@
 ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
 ;
 ; kernel void kernel1() {
-;   global int *FuncVar0 = 0;
-;   constant int *FuncVar1 = 0;
-;   local int *FuncVar2 = 0;
-;   private int *FuncVar3 = 0;
-;   int *FuncVar4 = 0;
+;   global int  addrspace(5)*FuncVar0 = 0;
+;   constant int  addrspace(5)*FuncVar1 = 0;
+;   local int  addrspace(5)*FuncVar2 = 0;
+;   private int  addrspace(5)*FuncVar3 = 0;
+;   int  addrspace(5)*FuncVar4 = 0;
 ; }
 
 ; CHECK:      DW_AT_name {{.*}}"FuncVar0"
@@ -53,21 +53,21 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata)
 
 define amdgpu_kernel void @kernel1() !dbg !7 {
 entry:
-  %FuncVar0 = alloca i32 addrspace(1)*, align 4
-  %FuncVar1 = alloca i32 addrspace(2)*, align 4
-  %FuncVar2 = alloca i32 addrspace(3)*, align 4
-  %FuncVar3 = alloca i32*, align 4
-  %FuncVar4 = alloca i32 addrspace(4)*, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %FuncVar0, metadata !10, metadata !13), !dbg !14
-  store i32 addrspace(1)* null, i32 addrspace(1)** %FuncVar0, align 4, !dbg !14
-  call void @llvm.dbg.declare(metadata i32 addrspace(2)** %FuncVar1, metadata !15, metadata !13), !dbg !16
-  store i32 addrspace(2)* null, i32 addrspace(2)** %FuncVar1, align 4, !dbg !16
-  call void @llvm.dbg.declare(metadata i32 addrspace(3)** %FuncVar2, metadata !17, metadata !13), !dbg !19
-  store i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*), i32 addrspace(3)** %FuncVar2, align 4, !dbg !19
-  call void @llvm.dbg.declare(metadata i32** %FuncVar3, metadata !20, metadata !13), !dbg !22
-  store i32* addrspacecast (i32 addrspace(4)* null to i32*), i32** %FuncVar3, align 4, !dbg !22
-  call void @llvm.dbg.declare(metadata i32 addrspace(4)** %FuncVar4, metadata !23, metadata !13), !dbg !24
-  store i32 addrspace(4)* null, i32 addrspace(4)** %FuncVar4, align 4, !dbg !24
+  %FuncVar0 = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  %FuncVar1 = alloca i32 addrspace(2)*, align 4, addrspace(5)
+  %FuncVar2 = alloca i32 addrspace(3)*, align 4, addrspace(5)
+  %FuncVar3 = alloca i32 addrspace(5)*, align 4, addrspace(5)
+  %FuncVar4 = alloca i32*, align 4, addrspace(5)
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %FuncVar0, metadata !10, metadata !13), !dbg !14
+  store i32 addrspace(1)* null, i32 addrspace(1)* addrspace(5)* %FuncVar0, align 4, !dbg !14
+  call void @llvm.dbg.declare(metadata i32 addrspace(2)* addrspace(5)* %FuncVar1, metadata !15, metadata !13), !dbg !16
+  store i32 addrspace(2)* null, i32 addrspace(2)* addrspace(5)* %FuncVar1, align 4, !dbg !16
+  call void @llvm.dbg.declare(metadata i32 addrspace(3)* addrspace(5)* %FuncVar2, metadata !17, metadata !13), !dbg !19
+  store i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* addrspace(5)* %FuncVar2, align 4, !dbg !19
+  call void @llvm.dbg.declare(metadata i32 addrspace(5)* addrspace(5)* %FuncVar3, metadata !20, metadata !13), !dbg !22
+  store i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %FuncVar3, align 4, !dbg !22
+  call void @llvm.dbg.declare(metadata i32* addrspace(5)* %FuncVar4, metadata !23, metadata !13), !dbg !24
+  store i32* null, i32* addrspace(5)* %FuncVar4, align 4, !dbg !24
   ret void, !dbg !25
 }
 
diff --git a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll
index a97d0186f46..692769b7bfe 100644
--- a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll
+++ b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll
@@ -7,7 +7,7 @@
 ; global int GlobA;
 ; global int GlobB;
 ;
-; kernel void kernel1(unsigned int ArgN, global int *ArgA, global int *ArgB) {
+; kernel void kernel1(unsigned int ArgN, global int  addrspace(5)*ArgA, global int  addrspace(5)*ArgB) {
 ;   ArgA[ArgN] += ArgB[ArgN];
 ; }
 
@@ -45,22 +45,22 @@ define amdgpu_kernel void @kernel1(
 ; CHECK-NEXT: DW_AT_name {{.*}}"ArgB"
     i32 addrspace(1)* %ArgB) !dbg !13 {
 entry:
-  %ArgN.addr = alloca i32, align 4
-  %ArgA.addr = alloca i32 addrspace(1)*, align 4
-  %ArgB.addr = alloca i32 addrspace(1)*, align 4
-  store i32 %ArgN, i32* %ArgN.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %ArgN.addr, metadata !22, metadata !23), !dbg !24
-  store i32 addrspace(1)* %ArgA, i32 addrspace(1)** %ArgA.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %ArgA.addr, metadata !25, metadata !23), !dbg !26
-  store i32 addrspace(1)* %ArgB, i32 addrspace(1)** %ArgB.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %ArgB.addr, metadata !27, metadata !23), !dbg !28
-  %0 = load i32 addrspace(1)*, i32 addrspace(1)** %ArgB.addr, align 4, !dbg !29
-  %1 = load i32, i32* %ArgN.addr, align 4, !dbg !30
+  %ArgN.addr = alloca i32, align 4, addrspace(5)
+  %ArgA.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  %ArgB.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  store i32 %ArgN, i32 addrspace(5)* %ArgN.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(5)* %ArgN.addr, metadata !22, metadata !23), !dbg !24
+  store i32 addrspace(1)* %ArgA, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgA.addr, metadata !25, metadata !23), !dbg !26
+  store i32 addrspace(1)* %ArgB, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgB.addr, metadata !27, metadata !23), !dbg !28
+  %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4, !dbg !29
+  %1 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !30
   %idxprom = zext i32 %1 to i64, !dbg !29
   %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %idxprom, !dbg !29
   %2 = load i32, i32 addrspace(1)* %arrayidx, align 4, !dbg !29
-  %3 = load i32 addrspace(1)*, i32 addrspace(1)** %ArgA.addr, align 4, !dbg !31
-  %4 = load i32, i32* %ArgN.addr, align 4, !dbg !32
+  %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4, !dbg !31
+  %4 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !32
   %idxprom1 = zext i32 %4 to i64, !dbg !31
   %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %idxprom1, !dbg !31
   %5 = load i32, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33
@@ -94,7 +94,7 @@ entry:
 !17 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64)
 !18 = !{i32 0, i32 1, i32 1}
 !19 = !{!"none", !"none", !"none"}
-!20 = !{!"uint", !"int*", !"int*"}
+!20 = !{!"uint", !"int addrspace(5)*", !"int addrspace(5)*"}
 !21 = !{!"", !"", !""}
 !22 = !DILocalVariable(name: "ArgN", arg: 1, scope: !13, file: !3, line: 4, type: !16)
 !23 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)