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| author | Tim Northover <tnorthover@apple.com> | 2017-05-30 21:28:57 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2017-05-30 21:28:57 +0000 |
| commit | fb26d9a2865e41320d0a891d35ed7d23e679815d (patch) | |
| tree | 4366c94beb1f63f28d5af2051de74871565df814 /llvm/test/CodeGen | |
| parent | 74480adafd0a2fc475bbed73372ce0da2a4ae3c1 (diff) | |
| download | bcm5719-llvm-fb26d9a2865e41320d0a891d35ed7d23e679815d.tar.gz bcm5719-llvm-fb26d9a2865e41320d0a891d35ed7d23e679815d.zip | |
MIR: remove explicit "noVRegs" property.
We can infer this from the incoming MIR, so there's no reason to
represent it with a special flag.
llvm-svn: 304246
Diffstat (limited to 'llvm/test/CodeGen')
6 files changed, 0 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir index 96436209451..c35d1719f84 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir @@ -13,7 +13,6 @@ name: main alignment: 2 exposesReturnsTwice: false -noVRegs: false legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-m0.mir b/llvm/test/CodeGen/AMDGPU/merge-m0.mir index 064db49924e..720642ad1dd 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-m0.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-m0.mir @@ -50,7 +50,6 @@ name: test alignment: 0 exposesReturnsTwice: false -noVRegs: false legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir index 0e9bc42565f..6577ef84867 100644 --- a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir +++ b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir @@ -190,7 +190,6 @@ name: foo alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false @@ -289,7 +288,6 @@ body: | name: bar alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir index 7831e51e315..7fb1afae912 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -39,7 +39,6 @@ name: l5 alignment: 2 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir index 89ed9872053..10606679134 100644 --- a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir +++ b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir @@ -39,7 +39,6 @@ name: Func alignment: 1 exposesReturnsTwice: false -noVRegs: true legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll index bc394f6e156..6c60aed67a7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-call.ll @@ -5,7 +5,6 @@ define void @test_void_return() { ; CHECK-LABEL: name: test_void_return ; CHECK: alignment: 4 ; CHECK-NEXT: exposesReturnsTwice: false -; CHECK-NEXT: noVRegs: false ; CHECK-NEXT: legalized: false ; CHECK-NEXT: regBankSelected: false ; CHECK-NEXT: selected: false |
