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| author | Zvi Rackover <zvi.rackover@intel.com> | 2017-04-11 21:16:59 +0000 |
|---|---|---|
| committer | Zvi Rackover <zvi.rackover@intel.com> | 2017-04-11 21:16:59 +0000 |
| commit | f720c036f4b1ac9178410b3d47c3543b9b529a65 (patch) | |
| tree | ccb1cf6f31cd75868101af268d04e4c8235e611a /llvm/test/CodeGen | |
| parent | 1ac9c98e6c40d9a1e6cb904b414161388af4a89c (diff) | |
| download | bcm5719-llvm-f720c036f4b1ac9178410b3d47c3543b9b529a65.tar.gz bcm5719-llvm-f720c036f4b1ac9178410b3d47c3543b9b529a65.zip | |
[DAGCombine] Add more test cases for shuffle of splat. NFC.
Tests added contain splat-masks with undef elements.
llvm-svn: 299988
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/shuffle-of-splat-multiuses.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/shuffle-of-splat-multiuses.ll b/llvm/test/CodeGen/X86/shuffle-of-splat-multiuses.ll index 38d45ca99eb..d46082f20a4 100644 --- a/llvm/test/CodeGen/X86/shuffle-of-splat-multiuses.ll +++ b/llvm/test/CodeGen/X86/shuffle-of-splat-multiuses.ll @@ -42,3 +42,59 @@ define <8 x float> @foo8(<8 x float> %v, <8 x float> *%p) nounwind { store <8 x float> %res, <8 x float>* %p ret <8 x float> %res1 } + +define <4 x i32> @undef_splatmask(<4 x i32> %v) nounwind { +; AVX2-LABEL: undef_splatmask: +; AVX2: # BB#0: +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,2,3] +; AVX2-NEXT: retq + %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 2, i32 undef> + %res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef> + ret <4 x i32> %res1 +} + +define <4 x i32> @undef_splatmask2(<4 x i32> %v) nounwind { +; AVX2-LABEL: undef_splatmask2: +; AVX2: # BB#0: +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] +; AVX2-NEXT: retq + %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 2, i32 undef> + %res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef> + ret <4 x i32> %res1 +} + +define <4 x i32> @undef_splatmask3(<4 x i32> %v) nounwind { +; AVX2-LABEL: undef_splatmask3: +; AVX2: # BB#0: +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,2,3] +; AVX2-NEXT: retq + %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 2, i32 undef> + %res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 3> + ret <4 x i32> %res1 +} + +define <4 x i32> @undef_splatmask4(<4 x i32> %v, <4 x i32>* %p) nounwind { +; AVX2-LABEL: undef_splatmask4: +; AVX2: # BB#0: +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] +; AVX2-NEXT: vmovdqa %xmm1, (%rdi) +; AVX2-NEXT: retq + %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 2, i32 undef> + %res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef> + store <4 x i32> %res, <4 x i32>* %p + ret <4 x i32> %res1 +} + +define <4 x i32> @undef_splatmask5(<4 x i32> %v, <4 x i32>* %p) nounwind { +; AVX2-LABEL: undef_splatmask5: +; AVX2: # BB#0: +; AVX2-NEXT: vpbroadcastq %xmm0, %xmm1 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] +; AVX2-NEXT: vmovdqa %xmm1, (%rdi) +; AVX2-NEXT: retq + %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef> + %res1 = shufflevector <4 x i32> %res, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 3> + store <4 x i32> %res, <4 x i32>* %p + ret <4 x i32> %res1 +} |
