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| author | Jyoti Allur <jyoti.allur@samsung.com> | 2015-01-23 09:10:03 +0000 |
|---|---|---|
| committer | Jyoti Allur <jyoti.allur@samsung.com> | 2015-01-23 09:10:03 +0000 |
| commit | f1d7050a2561547c3cad7d33f47f894d9ca4229a (patch) | |
| tree | dbb0fed4e928d19c09026b1c0ca73746217ac5af /llvm/test/CodeGen | |
| parent | 494acc597f9150da9608a5fe1131573c92cbdb01 (diff) | |
| download | bcm5719-llvm-f1d7050a2561547c3cad7d33f47f894d9ca4229a.tar.gz bcm5719-llvm-f1d7050a2561547c3cad7d33f47f894d9ca4229a.zip | |
This patch fixes issue with lowering below mentioned pattern :-
_foo:
smull r0, r1, r1, r0
smull r2, r3, r3, r2
adds r0, r2, r0
adc r1, r3, r1
bx lr
to
_foo:
smull r0, r1, r1, r0
smlal r0, r1, r3, r2
bx lr
llvm-svn: 226904
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/longMAC.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/longMAC.ll b/llvm/test/CodeGen/ARM/longMAC.ll index fed6ec02f32..3f30fd40b7e 100644 --- a/llvm/test/CodeGen/ARM/longMAC.ll +++ b/llvm/test/CodeGen/ARM/longMAC.ll @@ -75,3 +75,44 @@ define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) { %add = add i64 %mul, %c ret i64 %add } + +define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) { +;CHECK-LABEL: MACLongTest6: +;CHECK: smull r12, lr, r1, r0 +;CHECK: smlal r12, lr, r3, r2 + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %mul = mul nsw i64 %conv1, %conv + %conv2 = sext i32 %c to i64 + %conv3 = sext i32 %d to i64 + %mul4 = mul nsw i64 %conv3, %conv2 + %add = add nsw i64 %mul4, %mul + ret i64 %add +} + +define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest7: +;CHECK-NOT: smlal + %conv = sext i32 %lhs to i64 + %conv1 = sext i32 %rhs to i64 + %mul = mul nsw i64 %conv1, %conv + %shl = shl i64 %mul, 32 + %shr = lshr i64 %mul, 32 + %or = or i64 %shl, %shr + %add = add i64 %or, %acc + ret i64 %add +} + +define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest8: +;CHECK-NOT: smlal + %conv = zext i32 %lhs to i64 + %conv1 = zext i32 %rhs to i64 + %mul = mul nuw i64 %conv1, %conv + %and = and i64 %mul, 4294967295 + %shl = shl i64 %mul, 32 + %or = or i64 %and, %shl + %add = add i64 %or, %acc + ret i64 %add +} + |
