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| author | Javed Absar <javed.absar@arm.com> | 2016-10-18 09:08:54 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2016-10-18 09:08:54 +0000 |
| commit | e7c338081a8e5f145654781a58175f5edb3aa9d6 (patch) | |
| tree | 208ac227cae0719f00a23890a8d642ac0441db24 /llvm/test/CodeGen | |
| parent | 4ddc92b6cdcb1a15b8973fad366cd70a06446439 (diff) | |
| download | bcm5719-llvm-e7c338081a8e5f145654781a58175f5edb3aa9d6.tar.gz bcm5719-llvm-e7c338081a8e5f145654781a58175f5edb3aa9d6.zip | |
[ARM] Assign cost of scaling for Cortex-R52
This patch assigns cost of the scaling used in addressing for Cortex-R52.
On Cortex-R52 a negated register offset takes longer than a non-negated
register offset, in a register-offset addressing mode.
Differential Revision: http://reviews.llvm.org/D25670
Reviewer: jmolloy
llvm-svn: 284460
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll index d8c979c8cd6..c50e42b515c 100644 --- a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll +++ b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll @@ -1,8 +1,9 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; Should use scaled addressing mode. -; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53 -; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF ; Should not generate negated register offset define void @sintzero(i32* %a) nounwind { @@ -23,6 +24,5 @@ return: ; preds = %cond_next } ; CHECK: lsl{{.*}}#2] -; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2] -; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2] +; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2] |
