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| author | Geoff Berry <gberry@codeaurora.org> | 2016-11-21 22:51:10 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-11-21 22:51:10 +0000 |
| commit | e0bf52f3948dd1b6fdac1d08f1fcadf8211970ab (patch) | |
| tree | ba6362c2ee7656a026a9c6639d75f4aa095315b4 /llvm/test/CodeGen | |
| parent | 3e50a5be8f5259bc256f39830e72525dd9f90626 (diff) | |
| download | bcm5719-llvm-e0bf52f3948dd1b6fdac1d08f1fcadf8211970ab.tar.gz bcm5719-llvm-e0bf52f3948dd1b6fdac1d08f1fcadf8211970ab.zip | |
[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.
Summary:
When searching for load/store instructions to pair/merge don't treat
writes to WZR/XZR as clobbers since they don't change the value read
from WZR/XZR (which is always 0).
Reviewers: mcrosier, junbuml, jmolloy, t.p.northover
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D26921
llvm-svn: 287592
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir b/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir new file mode 100644 index 00000000000..75ad849e4f3 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/ldst-opt-zr-clobber.mir @@ -0,0 +1,27 @@ + +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s + +--- | + define i1 @no-clobber-zr(i64* %p, i64 %x) { ret i1 0 } +... +--- +# Check that write of xzr doesn't inhibit pairing of xzr stores since +# it isn't actually clobbered. Written as a MIR test to avoid +# schedulers reordering instructions such that SUBS doesn't appear +# between stores. +# CHECK-LABEL: name: no-clobber-zr +# CHECK: STPXi %xzr, %xzr, %x0, 0 +name: no-clobber-zr +body: | + bb.0: + liveins: %x0, %x1 + STRXui %xzr, %x0, 0 :: (store 8 into %ir.p) + dead %xzr = SUBSXri killed %x1, 0, 0, implicit-def %nzcv + %w8 = CSINCWr %wzr, %wzr, 1, implicit killed %nzcv + STRXui %xzr, killed %x0, 1 :: (store 8 into %ir.p) + %w0 = ORRWrs %wzr, killed %w8, 0 + RET %lr, implicit %w0 +... + + + |
