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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-20 12:28:43 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-20 12:28:43 +0000 |
| commit | dca383123fa560b0076c374d133e4059367c18bd (patch) | |
| tree | d0188fb3b41ee8d46ed25c9ef354ef378fadcee5 /llvm/test/CodeGen | |
| parent | 4a83f802cc00ef0ac6487722d5b0e1ef58cdb205 (diff) | |
| download | bcm5719-llvm-dca383123fa560b0076c374d133e4059367c18bd.tar.gz bcm5719-llvm-dca383123fa560b0076c374d133e4059367c18bd.zip | |
[Hexagon] Improve scheduling based on register pressure
Patch by Brendon Cahoon.
llvm-svn: 327975
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/swp-stages4.ll | 6 |
3 files changed, 7 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll index ca1c1747013..9e4366f3b41 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll @@ -13,9 +13,10 @@ define void @test_00(<64 x i8>* %p, <64 x i8>* %q) #0 { ; CHECK-LABEL: test_01: ; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0) ; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1) -; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2) ; CHECK: } ; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]]) +; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2) +; CHECK: } ; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]]) define void @test_01(<128 x i8>* %p, <128 x i8>* %q) #0 { %v0 = load <128 x i8>, <128 x i8>* %p, align 1 diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll index 19eb2d1fc67..2a6767c644a 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll +++ b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll @@ -16,8 +16,9 @@ entry: %cmp199 = icmp eq i16 %call197, 0 br i1 %cmp199, label %if.then200, label %if.else201 +; CHECK: = add ; CHECK-DAG: [[R4:r[0-9]+]] = add -; CHECK: p0 = cmp.eq(r0,#0) +; CHECK-DAG: p0 = cmp.eq(r0,#0) ; CHECK: if (!p0) [[R3:r[0-9]+]] = add(r{{[0-9]+}},#3) ; CHECK-DAG: if (!p0) memh(##t) = [[R3]] ; CHECK-DAG: if (p0) memh(##t) = [[R4]] diff --git a/llvm/test/CodeGen/Hexagon/swp-stages4.ll b/llvm/test/CodeGen/Hexagon/swp-stages4.ll index 9e101662249..9a0bb9e8f5a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages4.ll @@ -10,10 +10,10 @@ ; CHECK-NOT: r[[REG0]] = and(r[[REG1]],#255) ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: r[[REG0]] += add +; CHECK: = add(r{{[0-9]+}},r[[REG0]]) ; CHECK: = and -; CHECK: r[[REG2:[0-9]+]] = and -; CHECK: r[[REG0]]{{:[0-9]+}} = combine(r[[REG2]],{{r[0-9]+}}) +; CHECK: = and +; CHECK: r[[REG0]] = and ; CHECK: endloop ; Function Attrs: nounwind |
