[Hexagon] Enable the post-RA scheduler

The aggressive anti-dependency breaker can rename the restored callee-
saved registers. To prevent this, mark these registers are live on all
paths to the return/tail-call instructions, and add implicit use operands
for them to these instructions.

llvm-svn: 270898

4 files changed, 9 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/Hexagon/adde.ll b/llvm/test/CodeGen/Hexagon/adde.ll
index 4a88914dc6c..43ddb4307ef 100644
--- a/llvm/test/CodeGen/Hexagon/adde.ll
+++ b/llvm/test/CodeGen/Hexagon/adde.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
+; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
 
 ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
 ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
diff --git a/llvm/test/CodeGen/Hexagon/newvaluestore.ll b/llvm/test/CodeGen/Hexagon/newvaluestore.ll
index 13cbba2d08e..cc1ff00ecdc 100644
--- a/llvm/test/CodeGen/Hexagon/newvaluestore.ll
+++ b/llvm/test/CodeGen/Hexagon/newvaluestore.ll
@@ -1,22 +1,13 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
-; Check that we generate new value store packet in V4
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check that we generate new value store.
 
 @i = global i32 0, align 4
-@j = global i32 10, align 4
-@k = global i32 100, align 4
 
-define i32 @main() nounwind {
+define i32 @main(i32 %x, i32* %p) nounwind {
 entry:
 ; CHECK: memw(r{{[0-9]+}}+#{{[0-9]+}}) = r{{[0-9]+}}.new
-  %number1 = alloca i32, align 4
-  %number2 = alloca i32, align 4
-  %number3 = alloca i32, align 4
-  %0 = load i32 , i32 * @i, align 4
-  store i32 %0, i32* %number1, align 4
-  %1 = load i32 , i32 * @j, align 4
-  store i32 %1, i32* %number2, align 4
-  %2 = load i32 , i32 * @k, align 4
-  store i32 %2, i32* %number3, align 4
-  ret i32 %0
+  %t0 = load i32, i32* @i, align 4
+  store i32 %t0, i32* %p, align 4
+  ret i32 %x
 }
 
diff --git a/llvm/test/CodeGen/Hexagon/sube.ll b/llvm/test/CodeGen/Hexagon/sube.ll
index fab3dcaefa8..e1688984b61 100644
--- a/llvm/test/CodeGen/Hexagon/sube.ll
+++ b/llvm/test/CodeGen/Hexagon/sube.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s
+; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
 
 ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
 ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
diff --git a/llvm/test/CodeGen/Hexagon/v60Intrins.ll b/llvm/test/CodeGen/Hexagon/v60Intrins.ll
index 5f4f294c405..d0064c50e71 100644
--- a/llvm/test/CodeGen/Hexagon/v60Intrins.ll
+++ b/llvm/test/CodeGen/Hexagon/v60Intrins.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2  < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra  < %s | FileCheck %s
 
 ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}})
 ; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]*}})