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| author | Pete Cooper <peter_cooper@apple.com> | 2015-05-06 16:39:17 +0000 |
|---|---|---|
| committer | Pete Cooper <peter_cooper@apple.com> | 2015-05-06 16:39:17 +0000 |
| commit | d927c6eaf87ac128c320987c4c63dccae2fba4f3 (patch) | |
| tree | 6264fa192259856837358f109178e53c43139fa7 /llvm/test/CodeGen | |
| parent | aed5f3cf7e31886a373b5b62585fb88a6bd85167 (diff) | |
| download | bcm5719-llvm-d927c6eaf87ac128c320987c4c63dccae2fba4f3.tar.gz bcm5719-llvm-d927c6eaf87ac128c320987c4c63dccae2fba4f3.zip | |
[ARM] Fast-Isel was incorrectly selecting <2 x double> adds.
With neon enabled, we reach SelectBinaryFPOp and are able to get registers for a <2 x double> add.
However, we shouldn't actually attempt arithmetic on it as ARMIselLowering says "v2f64 is legal so that QR subregs can be extracted as f64 elements, but neither Neon nor VFP support any arithmetic operations on it."
This commit disables SelectBinaryFPOp for any vector types. There's already a FIXME to try handle neon. Doing so would require fixing this conditional which isn't safe for vectors 'VT == MVT::f64 || VT == MVT::i64'
llvm-svn: 236609
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fast-isel-vaddd.ll | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll b/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll new file mode 100644 index 00000000000..2aa269a9774 --- /dev/null +++ b/llvm/test/CodeGen/ARM/fast-isel-vaddd.ll @@ -0,0 +1,33 @@ +; RUN: llc %s -o - -verify-machineinstrs -fast-isel=true -mattr=+vfp4 -mattr=+neon | FileCheck %s + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +%union.DV = type { <2 x double> } + +; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds +; Check that we generate the 2 vaddd's we expect + +; CHECK: vadd.f64 +; CHECK: vadd.f64 + +define i32 @main(i32 %argc, i8** nocapture readnone %Argv, <2 x double> %tmp31) { +bb: + %Ad = alloca %union.DV, align 16 + %tmp32 = getelementptr inbounds %union.DV, %union.DV* %Ad, i32 0, i32 0 + %tmp33 = fadd <2 x double> %tmp31, %tmp31 + br label %bb37 + +bb37: ; preds = %bb37, %bb + %i.02 = phi i32 [ 0, %bb ], [ %tmp38, %bb37 ] + store <2 x double> %tmp33, <2 x double>* %tmp32, align 16 + %tmp38 = add nuw nsw i32 %i.02, 1 + %exitcond = icmp eq i32 %tmp38, 500000 + br i1 %exitcond, label %bb39, label %bb37 + +bb39: ; preds = %bb37 + call fastcc void @printDV(%union.DV* %Ad) + ret i32 0 +} + +declare hidden fastcc void @printDV(%union.DV* nocapture readonly) |
