[mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions

Differential Revision: http://reviews.llvm.org/D16719

llvm-svn: 272764

10 files changed, 1586 insertions, 43 deletions

diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index adf0692919a..59e847b8844 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -237,7 +237,7 @@ define i32 @one_f32(float %a, float %b) nounwind {
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]]
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
@@ -274,7 +274,7 @@ define i32 @ord_f32(float %a, float %b) nounwind {
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
@@ -481,7 +481,7 @@ define i32 @une_f32(float %a, float %b) nounwind {
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
@@ -756,7 +756,7 @@ define i32 @one_f64(double %a, double %b) nounwind {
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
@@ -793,7 +793,7 @@ define i32 @ord_f64(double %a, double %b) nounwind {
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
@@ -1000,7 +1000,7 @@ define i32 @une_f64(double %a, double %b) nounwind {
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
-; MMR6-DAG:      nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index c4121701ec1..9574d57c9ff 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -24,12 +24,23 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: and_i1:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i1 %a, %b
   ret i1 %r
@@ -39,7 +50,12 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: and_i8:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i8 %a, %b
   ret i8 %r
@@ -49,7 +65,12 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: and_i16:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $2, $4, $5
+
+  ; MM:           and16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = and i16 %a, %b
   ret i16 %r
@@ -64,6 +85,12 @@ entry:
   ; GP64:         and     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         and16   $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         and     $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = and i32 %a, %b
   ret i32 %r
 }
@@ -77,6 +104,13 @@ entry:
 
   ; GP64:         and     $2, $4, $5
 
+  ; MM32:         and16   $[[T0:[0-9]+]], $6
+  ; MM32:         and16   $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         and     $2, $4, $5
+
   %r = and i64 %a, %b
   ret i64 %r
 }
@@ -97,6 +131,573 @@ entry:
   ; GP64:         and     $2, $4, $6
   ; GP64:         and     $3, $5, $7
 
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         and16   $[[T1]], $4
+  ; MM32:         and16   $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         and16   $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         and16   $[[T3]], $7
+
+  ; MM64:         and     $2, $4, $6
+  ; MM64:         and     $3, $5, $7
+
   %r = and i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @and_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_4:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_4:
+
+  ; GP32:         andi    $2, $4, 4
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM:           andi16  $2, $4, 4
+
+  %r = and i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_4:
+
+  ; GP32:         andi    $3, $5, 4
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 4
+
+  ; MM32:         andi16  $3, $5, 4
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 4
+
+  %r = and i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_4:
+
+  ; GP32:         andi    $5, $7, 4
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 4
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 4
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 4
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 4, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_31(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_31:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 31, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_31(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i8 31, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_31(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i16 31, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_31(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_31:
+
+  ; GP32:         andi    $2, $4, 31
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM:           andi16  $2, $4, 31
+
+  %r = and i32 31, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_31(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_31:
+
+  ; GP32:         andi    $3, $5, 31
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 31
+
+  ; MM32:         andi16  $3, $5, 31
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 31
+
+  %r = and i64 31, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_31(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_31:
+
+  ; GP32:         andi    $5, $7, 31
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 31
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 31
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 31
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 31, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_255(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_255:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 255, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_255(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_255:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i8 255, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_255(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_255:
+
+  ; GP32:         andi    $2, $4, 255
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM:           andi16  $2, $4, 255
+
+  %r = and i16 255, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_255(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_255:
+
+  ; GP32:         andi    $2, $4, 255
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM:           andi16  $2, $4, 255
+
+  %r = and i32 255, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_255(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_255:
+
+  ; GP32:         andi    $3, $5, 255
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 255
+
+  ; MM32:         andi16  $3, $5, 255
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 255
+
+  %r = and i64 255, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_255(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_255:
+
+  ; GP32:         andi    $5, $7, 255
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 255
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 255
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 255
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 255, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_32768(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_32768:
+
+  ; GP32:         addiu  $2, $zero, 0
+
+  ; GP64:         addiu  $2, $zero, 0
+
+  ; MM:           lui    $2, 0
+
+  %r = and i1 32768, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_32768(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_32768:
+
+  ; GP32:         addiu  $2, $zero, 0
+
+  ; GP64:         addiu  $2, $zero, 0
+
+  ; MM:           lui    $2, 0
+
+  %r = and i8 32768, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_32768(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_32768:
+
+  ; GP32:         addiu  $[[T0:[0-9]+]], $zero, -32768
+  ; GP32:         and    $2, $4, $[[T0]]
+
+  ; GP64:         addiu  $[[T0:[0-9]+]], $zero, -32768
+  ; GP64:         and    $2, $4, $[[T0]]
+
+  ; MM:           addiu  $2, $zero, -32768
+  ; MM:           and16  $2, $4
+
+  %r = and i16 32768, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_32768(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_32768:
+
+  ; GP32:         andi    $2, $4, 32768
+
+  ; GP64:         andi    $2, $4, 32768
+
+  ; MM:           andi16  $2, $4, 32768
+
+  %r = and i32 32768, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_32768(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_32768:
+
+  ; GP32:         andi    $3, $5, 32768
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 32768
+
+  ; MM32:         andi16  $3, $5, 32768
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 32768
+
+  %r = and i64 32768, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_32768(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_32768:
+
+  ; GP32:         andi    $5, $7, 32768
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 32768
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi16  $5, $7, 32768
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 32768
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 32768, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_65(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_65:
+
+  ; ALL:          move    $2, $4
+
+  %r = and i1 65, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_65(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i8 65, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_65(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i16 65, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_65(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_65:
+
+  ; ALL:          andi    $2, $4, 65
+
+  %r = and i32 65, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_65(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_65:
+
+  ; GP32:         andi    $3, $5, 65
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 65
+
+  ; MM32:         andi    $3, $5, 65
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 65
+
+  %r = and i64 65, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_65(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_65:
+
+  ; GP32:         andi    $5, $7, 65
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 65
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi    $5, $7, 65
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 65
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 65, %b
+  ret i128 %r
+}
+
+define signext i1 @and_i1_256(i1 signext %b) {
+entry:
+; ALL-LABEL: and_i1_256:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i1 256, %b
+  ret i1 %r
+}
+
+define signext i8 @and_i8_256(i8 signext %b) {
+entry:
+; ALL-LABEL: and_i8_256:
+
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         addiu   $2, $zero, 0
+
+  ; MM:           lui     $2, 0
+
+  %r = and i8 256, %b
+  ret i8 %r
+}
+
+define signext i16 @and_i16_256(i16 signext %b) {
+entry:
+; ALL-LABEL: and_i16_256:
+
+  ; ALL:          andi    $2, $4, 256
+
+  %r = and i16 256, %b
+  ret i16 %r
+}
+
+define signext i32 @and_i32_256(i32 signext %b) {
+entry:
+; ALL-LABEL: and_i32_256:
+
+  ; ALL:          andi    $2, $4, 256
+
+  %r = and i32 256, %b
+  ret i32 %r
+}
+
+define signext i64 @and_i64_256(i64 signext %b) {
+entry:
+; ALL-LABEL: and_i64_256:
+
+  ; GP32:         andi    $3, $5, 256
+  ; GP32:         addiu   $2, $zero, 0
+
+  ; GP64:         andi    $2, $4, 256
+
+  ; MM32:         andi    $3, $5, 256
+  ; MM32:         lui     $2, 0
+
+  ; MM64:         andi    $2, $4, 256
+
+  %r = and i64 256, %b
+  ret i64 %r
+}
+
+define signext i128 @and_i128_256(i128 signext %b) {
+entry:
+; ALL-LABEL: and_i128_256:
+
+  ; GP32:         andi    $5, $7, 256
+  ; GP32:         addiu   $2, $zero, 0
+  ; GP32:         addiu   $3, $zero, 0
+  ; GP32:         addiu   $4, $zero, 0
+
+  ; GP64:         andi    $3, $5, 256
+  ; GP64:         daddiu  $2, $zero, 0
+
+  ; MM32:         andi    $5, $7, 256
+  ; MM32:         lui     $2, 0
+  ; MM32:         lui     $3, 0
+  ; MM32:         lui     $4, 0
+
+  ; MM64:         andi    $3, $5, 256
+  ; MM64:         daddiu  $2, $zero, 0
+
+  %r = and i128 256, %b
+  ret i128 %r
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index 066fcbd321b..d3c567b3c8a 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -159,9 +159,9 @@ entry:
   ; MMR6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
   ; MMR6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
   ; MMR6:       srlv      $[[T6:[0-9]+]], $5, $7
-  ; MMR6:       not       $[[T7:[0-9]+]], $7
-  ; MMR6:       sll16     $[[T8:[0-9]+]], $4, 1
-  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; MMR6:       sll16     $[[T7:[0-9]+]], $4, 1
+  ; MMR6:       not16     $[[T8:[0-9]+]], $7
+  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T7]], $[[T8]]
   ; MMR6:       or16      $[[T10:[0-9]+]], $[[T6]]
   ; MMR6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
   ; MMR6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index 9c61aeb98ef..aa162595e7b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -147,9 +147,9 @@ entry:
   ; MMR3:       movn      $2, $[[T8]], $[[T6]]
 
   ; MMR6:       srlv      $[[T0:[0-9]+]], $5, $7
-  ; MMR6:       not       $[[T1:[0-9]+]], $7
-  ; MMR6:       sll16     $[[T2:[0-9]+]], $4, 1
-  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR6:       not16     $[[T2:[0-9]+]], $7
+  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/not.ll b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
new file mode 100644
index 00000000000..531a1b0447d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
@@ -0,0 +1,241 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
+
+define signext i1 @not_i1(i1 signext %a) {
+entry:
+; ALL-LABEL: not_i1:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i1 %a, -1
+  ret i1 %r
+}
+
+define signext i8 @not_i8(i8 signext %a) {
+entry:
+; ALL-LABEL: not_i8:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i8 %a, -1
+  ret i8 %r
+}
+
+define signext i16 @not_i16(i16 signext %a) {
+entry:
+; ALL-LABEL: not_i16:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i16 %a, -1
+  ret i16 %r
+}
+
+define signext i32 @not_i32(i32 signext %a) {
+entry:
+; ALL-LABEL: not_i32:
+
+  ; GP32:         not     $2, $4
+
+  ; GP64:         not     $2, $4
+
+  ; MM:           not16   $2, $4
+
+  %r = xor i32 %a, -1
+  ret i32 %r
+}
+
+define signext i64 @not_i64(i64 signext %a) {
+entry:
+; ALL-LABEL: not_i64:
+
+  ; GP32:         not     $2, $4
+  ; GP32:         not     $3, $5
+
+  ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; GP64:         xor     $2, $4, $[[T0]]
+
+  ; MM32:         not16   $2, $4
+  ; MM32:         not16   $3, $5
+
+  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; MM64:         xor     $2, $4, $[[T0]]
+
+  %r = xor i64 %a, -1
+  ret i64 %r
+}
+
+define signext i128 @not_i128(i128 signext %a) {
+entry:
+; ALL-LABEL: not_i128:
+
+  ; GP32:         not     $2, $4
+  ; GP32:         not     $3, $5
+  ; GP32:         not     $4, $6
+  ; GP32:         not     $5, $7
+
+  ; GP64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; GP64:         xor     $2, $4, $[[T0]]
+  ; GP64:         xor     $3, $5, $[[T0]]
+
+  ; MM32:         not16   $2, $4
+  ; MM32:         not16   $3, $5
+  ; MM32:         not16   $4, $6
+  ; MM32:         not16   $5, $7
+
+  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
+  ; MM64:         xor     $2, $4, $[[T0]]
+  ; MM64:         xor     $3, $5, $[[T0]]
+
+  %r = xor i128 %a, -1
+  ret i128 %r
+}
+
+define signext i1 @nor_i1(i1 signext %a, i1 signext %b) {
+entry:
+; ALL-LABEL: nor_i1:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i1 %b, %a
+  %r = xor i1 %or, -1
+  ret i1 %r
+}
+
+define signext i8 @nor_i8(i8 signext %a, i8 signext %b) {
+entry:
+; ALL-LABEL: nor_i8:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i8 %b, %a
+  %r = xor i8 %or, -1
+  ret i8 %r
+}
+
+define signext i16 @nor_i16(i16 signext %a, i16 signext %b) {
+entry:
+; ALL-LABEL: nor_i16:
+
+  ; ALL:          nor     $2, $5, $4
+
+  %or = or i16 %b, %a
+  %r = xor i16 %or, -1
+  ret i16 %r
+}
+
+define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
+entry:
+; ALL-LABEL: nor_i32:
+
+  ; GP32:         nor     $2, $5, $4
+
+  ; GP64:         or      $[[T0:[0-9]+]], $5, $4
+  ; GP64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
+  ; GP64:         not     $2, $[[T1]]
+
+  ; MM32:         nor     $2, $5, $4
+
+  ; MM64:         or      $[[T0:[0-9]+]], $5, $4
+  ; MM64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
+  ; MM64:         not16   $2, $[[T1]]
+
+  %or = or i32 %b, %a
+  %r = xor i32 %or, -1
+  ret i32 %r
+}
+
+
+define signext i64 @nor_i64(i64 signext %a, i64 signext %b) {
+entry:
+; ALL-LABEL: nor_i64:
+
+  ; GP32:         nor     $2, $6, $4
+  ; GP32:         nor     $3, $7, $5
+
+  ; GP64:         nor     $2, $5, $4
+
+  ; MM32:         nor     $2, $6, $4
+  ; MM32:         nor     $3, $7, $5
+
+  ; MM64:         nor     $2, $5, $4
+
+  %or = or i64 %b, %a
+  %r = xor i64 %or, -1
+  ret i64 %r
+}
+
+define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
+entry:
+; ALL-LABEL: nor_i128:
+
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
+  ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
+  ; GP32:         nor     $2, $[[T2]], $4
+  ; GP32:         nor     $3, $[[T1]], $5
+  ; GP32:         nor     $4, $[[T0]], $6
+  ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; GP32:         nor     $5, $[[T3]], $7
+
+  ; GP64:         nor     $2, $6, $4
+  ; GP64:         nor     $3, $7, $5
+
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         nor     $2, $[[T1]], $4
+  ; MM32:         nor     $3, $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         nor     $4, $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         nor     $5, $[[T3]], $7
+
+  ; MM64:         nor     $2, $6, $4
+  ; MM64:         nor     $3, $7, $5
+
+  %or = or i128 %b, %a
+  %r = xor i128 %or, -1
+  ret i128 %r
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 8509d6ce93f..a83992839cd 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -24,12 +24,23 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: or_i1:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i1 %a, %b
   ret i1 %r
@@ -39,7 +50,12 @@ define signext i8 @or_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: or_i8:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i8 %a, %b
   ret i8 %r
@@ -49,7 +65,12 @@ define signext i16 @or_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: or_i16:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
+
+  ; GP64:         or      $2, $4, $5
+
+  ; MM:           or16    $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = or i16 %a, %b
   ret i16 %r
@@ -59,12 +80,18 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
+  ; GP32:         or      $2, $4, $5
 
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         or      $[[T0:[0-9]+]], $4, $5
   ; FIXME: The sll instruction below is redundant.
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         or16    $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         or      $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = or i32 %a, %b
   ret i32 %r
 }
@@ -73,10 +100,17 @@ define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: or_i64:
 
-  ; GP32:         or     $2, $4, $6
-  ; GP32:         or     $3, $5, $7
+  ; GP32:         or      $2, $4, $6
+  ; GP32:         or      $3, $5, $7
+
+  ; GP64:         or      $2, $4, $5
 
-  ; GP64:         or     $2, $4, $5
+  ; MM32:         or16    $[[T0:[0-9]+]], $6
+  ; MM32:         or16    $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         or      $2, $4, $5
 
   %r = or i64 %a, %b
   ret i64 %r
@@ -86,18 +120,557 @@ define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: or_i128:
 
-  ; GP32:         lw     $[[T0:[0-9]+]], 24($sp)
-  ; GP32:         lw     $[[T1:[0-9]+]], 20($sp)
-  ; GP32:         lw     $[[T2:[0-9]+]], 16($sp)
-  ; GP32:         or     $2, $4, $[[T2]]
-  ; GP32:         or     $3, $5, $[[T1]]
-  ; GP32:         or     $4, $6, $[[T0]]
-  ; GP32:         lw     $[[T3:[0-9]+]], 28($sp)
-  ; GP32:         or     $5, $7, $[[T3]]
+  ; GP32:         lw      $[[T0:[0-9]+]], 24($sp)
+  ; GP32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; GP32:         lw      $[[T2:[0-9]+]], 16($sp)
+  ; GP32:         or      $2, $4, $[[T2]]
+  ; GP32:         or      $3, $5, $[[T1]]
+  ; GP32:         or      $4, $6, $[[T0]]
+  ; GP32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; GP32:         or      $5, $7, $[[T3]]
+
+  ; GP64:         or      $2, $4, $6
+  ; GP64:         or      $3, $5, $7
+
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         or16    $[[T1]], $4
+  ; MM32:         or16    $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         or16    $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         or16    $[[T3]], $7
 
-  ; GP64:         or     $2, $4, $6
-  ; GP64:         or     $3, $5, $7
+  ; MM64:         or      $2, $4, $6
+  ; MM64:         or      $3, $5, $7
 
   %r = or i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @or_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_4:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_4:
+
+  ; ALL:          ori     $2, $4, 4
+
+  %r = or i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_4:
+
+  ; GP32:         ori     $3, $5, 4
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 4
+
+  ; MM32:         ori     $3, $5, 4
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 4
+
+  %r = or i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_4:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 4
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 4
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 4
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 4
+  ; MM64:         move    $2, $4
+
+  %r = or i128 4, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_31(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_31:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 31, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_31(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i8 31, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_31(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i16 31, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_31(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_31:
+
+  ; ALL:          ori     $2, $4, 31
+
+  %r = or i32 31, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_31(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_31:
+
+  ; GP32:         ori     $3, $5, 31
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 31
+
+  ; MM32:         ori     $3, $5, 31
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 31
+
+  %r = or i64 31, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_31(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_31:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 31
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 31
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 31
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 31
+  ; MM64:         move    $2, $4
+
+  %r = or i128 31, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_255(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_255:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 255, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_255(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_255:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i8 255, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_255(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_255:
+
+  ; ALL:          ori     $2, $4, 255
+
+  %r = or i16 255, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_255(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_255:
+
+  ; ALL:          ori     $2, $4, 255
+
+  %r = or i32 255, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_255(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_255:
+
+  ; GP32:         ori     $3, $5, 255
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 255
+
+  ; MM32:         ori     $3, $5, 255
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 255
+
+  %r = or i64 255, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_255(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_255:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 255
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 255
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 255
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 255
+  ; MM64:         move    $2, $4
+
+  %r = or i128 255, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_32768(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_32768:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 32768, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_32768(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_32768:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i8 32768, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_32768(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_32768:
+
+  ; GP32:         addiu   $[[T0:[0-9]+]], $zero, -32768
+  ; GP32:         or      $2, $4, $[[T0]]
+
+  ; GP64:         addiu   $[[T0:[0-9]+]], $zero, -32768
+  ; GP64:         or      $2, $4, $[[T0]]
+
+  ; MM:           addiu   $2, $zero, -32768
+  ; MM:           or16    $2, $4
+
+  %r = or i16 32768, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_32768(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_32768:
+
+  ; ALL:          ori     $2, $4, 32768
+
+  %r = or i32 32768, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_32768(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_32768:
+
+  ; GP32:         ori     $3, $5, 32768
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 32768
+
+  ; MM32:         ori     $3, $5, 32768
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 32768
+
+  %r = or i64 32768, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_32768(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_32768:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 32768
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 32768
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 32768
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 32768
+  ; MM64:         move    $2, $4
+
+  %r = or i128 32768, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_65(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_65:
+
+  ; GP32:         addiu   $2, $zero, -1
+
+  ; GP64:         addiu   $2, $zero, -1
+
+  ; MM:           li16    $2, -1
+
+  %r = or i1 65, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_65(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i8 65, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_65(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i16 65, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_65(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_65:
+
+  ; ALL:          ori     $2, $4, 65
+
+  %r = or i32 65, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_65(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_65:
+
+  ; GP32:         ori     $3, $5, 65
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 65
+
+  ; MM32:         ori     $3, $5, 65
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 65
+
+  %r = or i64 65, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_65(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_65:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 65
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 65
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 65
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 65
+  ; MM64:         move    $2, $4
+
+  %r = or i128 65, %b
+  ret i128 %r
+}
+
+define signext i1 @or_i1_256(i1 signext %b) {
+entry:
+; ALL-LABEL: or_i1_256:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i1 256, %b
+  ret i1 %r
+}
+
+define signext i8 @or_i8_256(i8 signext %b) {
+entry:
+; ALL-LABEL: or_i8_256:
+
+  ; ALL:          move    $2, $4
+
+  %r = or i8 256, %b
+  ret i8 %r
+}
+
+define signext i16 @or_i16_256(i16 signext %b) {
+entry:
+; ALL-LABEL: or_i16_256:
+
+  ; ALL:          ori     $2, $4, 256
+
+  %r = or i16 256, %b
+  ret i16 %r
+}
+
+define signext i32 @or_i32_256(i32 signext %b) {
+entry:
+; ALL-LABEL: or_i32_256:
+
+  ; ALL:          ori     $2, $4, 256
+
+  %r = or i32 256, %b
+  ret i32 %r
+}
+
+define signext i64 @or_i64_256(i64 signext %b) {
+entry:
+; ALL-LABEL: or_i64_256:
+
+  ; GP32:         ori     $3, $5, 256
+  ; GP32:         move    $2, $4
+
+  ; GP64:         ori     $2, $4, 256
+
+  ; MM32:         ori     $3, $5, 256
+  ; MM32:         move    $2, $4
+
+  ; MM64:         ori     $2, $4, 256
+
+  %r = or i64 256, %b
+  ret i64 %r
+}
+
+define signext i128 @or_i128_256(i128 signext %b) {
+entry:
+; ALL-LABEL: or_i128_256:
+
+  ; GP32:         ori     $[[T0:[0-9]+]], $7, 256
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         ori     $3, $5, 256
+  ; GP64:         move    $2, $4
+
+  ; MM32:         ori     $[[T0:[0-9]+]], $7, 256
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         ori     $3, $5, 256
+  ; MM64:         move    $2, $4
+
+  %r = or i128 256, %b
+  ret i128 %r
+}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 3962f9d2f1c..0182847e129 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -338,8 +338,7 @@ entry:
 
   ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
   ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; 32R6:       not       $[[T0]], $[[T0]]
-  ; MM32R6:     nor       $[[T0]], $[[T0]], $zero
+  ; SEL-32:     not       $[[T0]], $[[T0]]
   ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
   ; SEL-32:     sel.d     $f0, $f14, $f12
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 3816727e0d3..0b76956c8b4 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -315,8 +315,7 @@ entry:
 
   ; SEL-32:     cmp.ueq.s $f0, $f12, $f14
   ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; 32R6:       not       $[[T0]], $[[T0]]
-  ; MM32R6:     nor       $[[T0]], $[[T0]], $zero
+  ; SEL-32:     not       $[[T0]], $[[T0]]
   ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
   ; SEL-32:     sel.s     $f0, $f14, $f12
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
index 1e022c91192..b74af353aab 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -163,9 +163,9 @@ entry:
   ; MMR3:       movn      $3, $[[T8]], $[[T6]]
 
   ; MMR6:       sllv      $[[T0:[0-9]+]], $4, $7
-  ; MMR6:       not       $[[T1:[0-9]+]], $7
-  ; MMR6:       srl16     $[[T2:[0-9]+]], $5, 1
-  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       srl16     $[[T1:[0-9]+]], $5, 1
+  ; MMR6:       not16     $[[T2:[0-9]+]], $7
+  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
index d3cc5748489..1104ba1b5b4 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -24,12 +24,23 @@
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MM64
 
 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: xor_i1:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i1 %a, %b
   ret i1 %r
@@ -39,7 +50,12 @@ define signext i8 @xor_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: xor_i8:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i8 %a, %b
   ret i8 %r
@@ -49,7 +65,12 @@ define signext i16 @xor_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: xor_i16:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $2, $4, $5
+
+  ; MM:           xor16   $[[T0:[0-9]+]], $5
+  ; MM:           move    $2, $[[T0]]
 
   %r = xor i16 %a, %b
   ret i16 %r
@@ -64,6 +85,12 @@ entry:
   ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
   ; GP64:         sll     $2, $[[T0]], 0
 
+  ; MM32:         xor16   $[[T0:[0-9]+]], $5
+  ; MM32:         move    $2, $[[T0]]
+
+  ; MM64:         xor     $[[T0:[0-9]+]], $4, $5
+  ; MM64:         sll     $2, $[[T0]], 0
+
   %r = xor i32 %a, %b
   ret i32 %r
 }
@@ -77,6 +104,13 @@ entry:
 
   ; GP64:         xor     $2, $4, $5
 
+  ; MM32:         xor16   $[[T0:[0-9]+]], $6
+  ; MM32:         xor16   $[[T1:[0-9]+]], $7
+  ; MM32:         move    $2, $[[T0]]
+  ; MM32:         move    $3, $[[T1]]
+
+  ; MM64:         xor     $2, $4, $5
+
   %r = xor i64 %a, %b
   ret i64 %r
 }
@@ -97,6 +131,102 @@ entry:
   ; GP64:         xor     $2, $4, $6
   ; GP64:         xor     $3, $5, $7
 
+  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; MM32:         xor16   $[[T1]], $4
+  ; MM32:         xor16   $[[T0]], $5
+  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
+  ; MM32:         xor16   $[[T2]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         xor16   $[[T3]], $7
+
+  ; MM64:         xor     $2, $4, $6
+  ; MM64:         xor     $3, $5, $7
+
   %r = xor i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @xor_i1_4(i1 signext %b) {
+entry:
+; ALL-LABEL: xor_i1_4:
+
+  ; ALL:          move    $2, $4
+
+  %r = xor i1 4, %b
+  ret i1 %r
+}
+
+define signext i8 @xor_i8_4(i8 signext %b) {
+entry:
+; ALL-LABEL: xor_i8_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i8 4, %b
+  ret i8 %r
+}
+
+define signext i16 @xor_i16_4(i16 signext %b) {
+entry:
+; ALL-LABEL: xor_i16_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i16 4, %b
+  ret i16 %r
+}
+
+define signext i32 @xor_i32_4(i32 signext %b) {
+entry:
+; ALL-LABEL: xor_i32_4:
+
+  ; ALL:          xori    $2, $4, 4
+
+  %r = xor i32 4, %b
+  ret i32 %r
+}
+
+define signext i64 @xor_i64_4(i64 signext %b) {
+entry:
+; ALL-LABEL: xor_i64_4:
+
+  ; GP32:         xori    $3, $5, 4
+  ; GP32:         move    $2, $4
+
+  ; GP64:         xori    $2, $4, 4
+
+  ; MM32:         xori    $3, $5, 4
+  ; MM32:         move    $2, $4
+
+  ; MM64:         xori    $2, $4, 4
+
+  %r = xor i64 4, %b
+  ret i64 %r
+}
+
+define signext i128 @xor_i128_4(i128 signext %b) {
+entry:
+; ALL-LABEL: xor_i128_4:
+
+  ; GP32:         xori    $[[T0:[0-9]+]], $7, 4
+  ; GP32:         move    $2, $4
+  ; GP32:         move    $3, $5
+  ; GP32:         move    $4, $6
+  ; GP32:         move    $5, $[[T0]]
+
+  ; GP64:         xori    $3, $5, 4
+  ; GP64:         move    $2, $4
+
+  ; MM32:         xori    $[[T0:[0-9]+]], $7, 4
+  ; MM32:         move    $2, $4
+  ; MM32:         move    $3, $5
+  ; MM32:         move    $4, $6
+  ; MM32:         move    $5, $[[T0]]
+
+  ; MM64:         xori    $3, $5, 4
+  ; MM64:         move    $2, $4
+
+  %r = xor i128 4, %b
+  ret i128 %r
+}