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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-20 13:49:52 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-09-20 13:49:52 +0000 |
| commit | d202ad15c11950c71b8379ae3e2db4892b5d9d7b (patch) | |
| tree | a0aa53c665053428c37db712455f52d03334eb79 /llvm/test/CodeGen | |
| parent | 47f22026b5080cad4afef3eecb1c3c6138b24003 (diff) | |
| download | bcm5719-llvm-d202ad15c11950c71b8379ae3e2db4892b5d9d7b.tar.gz bcm5719-llvm-d202ad15c11950c71b8379ae3e2db4892b5d9d7b.zip | |
[X86][SSE] Add PR22415 test case
llvm-svn: 313755
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll index f1c994d2f6c..4b6c8179487 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll @@ -688,3 +688,25 @@ define <16 x i8> @constant_fold_pshufb_2() { %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 2, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) ret <16 x i8> %1 } + +define i32 @PR22415(double %a0) { +; SSE-LABEL: PR22415: +; SSE: # BB#0: +; SSE-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,u,u,u,u,u,u,u,u,u,u,u,u,u] +; SSE-NEXT: movd %xmm0, %eax +; SSE-NEXT: andl $16777215, %eax # imm = 0xFFFFFF +; SSE-NEXT: retq +; +; AVX-LABEL: PR22415: +; AVX: # BB#0: +; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: andl $16777215, %eax # imm = 0xFFFFFF +; AVX-NEXT: retq + %1 = bitcast double %a0 to <8 x i8> + %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 undef> + %3 = shufflevector <4 x i8> %2, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> + %4 = bitcast <3 x i8> %3 to i24 + %5 = zext i24 %4 to i32 + ret i32 %5 +} |
