[ARM] Support for v4f16 and v8f16 vectors

This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.

Differential Revision: https://reviews.llvm.org/D44538

llvm-svn: 327839

2 files changed, 60 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-1op.ll b/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-1op.ll
new file mode 100644
index 00000000000..f95def9d4d6
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-1op.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon  -float-abi=hard   | FileCheck %s --check-prefixes=CHECK,CHECK-HARD
+; RUN: llc < %s -mtriple=armeb-none-eabi -mattr=+v8.2a,+fullfp16,+neon  -float-abi=hard   | FileCheck %s --check-prefixes=CHECK,CHECK-HARD-BE
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon  | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP
+; RUN: llc < %s -mtriple=armeb-none-eabi -mattr=+v8.2a,+fullfp16,+neon  | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-BE
+
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
+
+define dso_local <8 x half> @t_vabsq_f16(<8 x half> %a) {
+; CHECK-LABEL:      t_vabsq_f16:
+
+; CHECK-HARD:         vabs.f16  q0, q0
+; CHECK-HARD-NEXT:    bx  lr
+
+; CHECK-HARD-BE:      vrev64.16 [[Q8:q[0-9]+]], q0
+; CHECK-HARD-BE-NEXT: vabs.f16  [[Q8]], [[Q8]]
+; CHECK-HARD-BE-NEXT: vrev64.16 q0, [[Q8]]
+; CHECK-HARD-BE-NEXT: bx  lr
+
+; CHECK-SOFTFP:       vmov  d{{.*}}, r2, r3
+; CHECK-SOFTFP:       vmov  d{{.*}}, r0, r1
+; CHECK-SOFTFP:       vabs.f16  q{{.*}}, q{{.*}}
+; CHECK-SOFTFP:       vmov  r0, r1, d{{.*}}
+; CHECK-SOFTFP:       vmov  r2, r3, d{{.*}}
+; CHECK-SOFTFP:       bx  lr
+
+; CHECK-SOFTFP-BE:    vmov  [[D17:d[0-9]+]], r3, r2
+; CHECK-SOFTFP-BE:    vmov  [[D16:d[0-9]+]], r1, r0
+; CHECK-SOFTFP-BE:    vrev64.16 [[Q8:q[0-9]+]], [[Q8]]
+; CHECK-SOFTFP-BE:    vabs.f16  [[Q8]], [[Q8]]
+; CHECK-SOFTFP-BE:    vrev64.16 [[Q8]], [[Q8]]
+; CHECK-SOFTFP-BE:    vmov  r1, r0, [[D16]]
+; CHECK-SOFTFP-BE:    vmov  r3, r2, [[D17]]
+; CHECK-SOFTFP-BE:    bx  lr
+
+entry:
+  %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) #3
+  ret <8 x half> %vabs1.i
+}
+
diff --git a/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-2op.ll b/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-2op.ll
new file mode 100644
index 00000000000..c1ada259419
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp16-intrinsic-vector-2op.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon  -float-abi=hard   | FileCheck %s --check-prefixes=CHECK,CHECK-HARD
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon  | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP
+
+declare <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half>, <4 x half>)
+
+define dso_local <4 x half> @t_vpadd_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK:   t_vpadd_f16:
+
+; CHECK-HARD:       vpadd.f16 d0, d0, d1
+; CHECK-HARD-NEXT:  bx  lr
+
+; CHECK-SOFTFP:     vmov  [[D1:d[0-9]+]], r2, r3
+; CHECK-SOFTFP:     vmov  [[D2:d[0-9]+]], r0, r1
+; CHECK-SOFTFP:     vpadd.f16 [[D3:d[0-9]+]], [[D2]], [[D1]]
+; CHECK-SOFTFP:     vmov  r0, r1, [[D3]]
+; CHECK-SOFTFP:     bx  lr
+
+entry:
+  %vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x half> %vpadd_v2.i
+}