[X86 fast-isel] Constrain the index reg class to not include SP.

The index reg on instructions with complex address modes is a GPR64_NOSP.  Constrain it to appease the machine verifier.

llvm-svn: 236557

1 files changed, 25 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll b/llvm/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll
new file mode 100644
index 00000000000..c2534f72bd0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fast-isel-constrain-store-indexreg.ll
@@ -0,0 +1,25 @@
+; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-unknown"
+
+@TheArray = external global [100000 x double], align 16
+
+; This test ensures, via the machine verifier, that the register class for the
+; index of the double store is correctly constrained to not include SP.
+
+; CHECK: movsd
+
+define i32 @main(i32* %i, double %tmpv) {
+bb:
+  br label %bb7
+
+bb7:                                              ; preds = %bb7, %bb
+  %storemerge = phi i32 [ 0, %bb ], [ %tmp19, %bb7 ]
+  %tmp15 = zext i32 %storemerge to i64
+  %tmp16 = getelementptr inbounds [100000 x double], [100000 x double]* @TheArray, i64 0, i64 %tmp15
+  store double %tmpv, double* %tmp16, align 8
+  %tmp18 = load i32, i32* %i, align 4
+  %tmp19 = add i32 %tmp18, 1
+  br label %bb7
+}