[SystemZ] Add CodeGen support for v2f64

This adds ABI and CodeGen support for the v2f64 type, which is natively
supported by z13 instructions.

Based on a patch by Richard Sandiford.

llvm-svn: 236522

34 files changed, 1381 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/SystemZ/vec-abs-05.ll b/llvm/test/CodeGen/SystemZ/vec-abs-05.ll
new file mode 100644
index 00000000000..89142b21854
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-abs-05.ll
@@ -0,0 +1,24 @@
+; Test v2f64 absolute.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
+
+; Test a plain absolute.
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vflpdb %v24, %v24
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
+
+; Test a negative absolute.
+define <2 x double> @f2(<2 x double> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vflndb %v24, %v24
+; CHECK: br %r14
+  %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val)
+  %ret = fsub <2 x double> <double -0.0, double -0.0>, %abs
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-add-01.ll b/llvm/test/CodeGen/SystemZ/vec-add-01.ll
index a59a8da1cf8..1de2aa2a1b9 100644
--- a/llvm/test/CodeGen/SystemZ/vec-add-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-add-01.ll
@@ -37,3 +37,13 @@ define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
   %ret = add <2 x i64> %val1, %val2
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 addition.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfadb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fadd <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-cmp-06.ll b/llvm/test/CodeGen/SystemZ/vec-cmp-06.ll
new file mode 100644
index 00000000000..bdb8744631a
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-cmp-06.ll
@@ -0,0 +1,337 @@
+; Test v2f64 comparisons.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test oeq.
+define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f1:
+; CHECK: vfcedb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test one.
+define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f2:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vo %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ogt.
+define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f3:
+; CHECK: vfchdb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test oge.
+define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f4:
+; CHECK: vfchedb %v24, %v26, %v28
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ole.
+define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfchedb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test olt.
+define <2 x i64> @f6(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vfchdb %v24, %v28, %v26
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ueq.
+define <2 x i64> @f7(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vno %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test une.
+define <2 x i64> @f8(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f8:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ugt.
+define <2 x i64> @f9(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f9:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test uge.
+define <2 x i64> @f10(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f10:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v28, %v26
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ule.
+define <2 x i64> @f11(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f11:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ult.
+define <2 x i64> @f12(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v28
+; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test ord.
+define <2 x i64> @f13(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f13:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vo %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test uno.
+define <2 x i64> @f14(<2 x i64> %dummy, <2 x double> %val1,
+                      <2 x double> %val2) {
+; CHECK-LABEL: f14:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v26, %v28
+; CHECK: vno %v24, [[REG1]], [[REG2]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <2 x double> %val1, %val2
+  %ret = sext <2 x i1> %cmp to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+; Test oeq selects.
+define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f15:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oeq <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test one selects.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f16:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp one <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ogt selects.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f17:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ogt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test oge selects.
+define <2 x double> @f18(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f18:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp oge <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ole selects.
+define <2 x double> @f19(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f19:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ole <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test olt selects.
+define <2 x double> @f20(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f20:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp olt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ueq selects.
+define <2 x double> @f21(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f21:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ueq <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test une selects.
+define <2 x double> @f22(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f22:
+; CHECK: vfcedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp une <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ugt selects.
+define <2 x double> @f23(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f23:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ugt <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test uge selects.
+define <2 x double> @f24(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f24:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v26, %v24
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uge <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ule selects.
+define <2 x double> @f25(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f25:
+; CHECK: vfchdb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ule <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ult selects.
+define <2 x double> @f26(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f26:
+; CHECK: vfchedb [[REG:%v[0-9]+]], %v24, %v26
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ult <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test ord selects.
+define <2 x double> @f27(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f27:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp ord <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
+
+; Test uno selects.
+define <2 x double> @f28(<2 x double> %val1, <2 x double> %val2,
+                         <2 x double> %val3, <2 x double> %val4) {
+; CHECK-LABEL: f28:
+; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v26, %v24
+; CHECK-DAG: vfchedb [[REG2:%v[0-9]+]], %v24, %v26
+; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
+; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
+; CHECK-NEXT: br %r14
+  %cmp = fcmp uno <2 x double> %val1, %val2
+  %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-const-06.ll b/llvm/test/CodeGen/SystemZ/vec-const-06.ll
new file mode 100644
index 00000000000..be53a0581ec
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-const-06.ll
@@ -0,0 +1,43 @@
+; Test vector byte masks, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test an all-zeros vector.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgbm %v24, 0
+; CHECK: br %r14
+  ret <2 x double> zeroinitializer
+}
+
+; Test an all-ones vector.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgbm %v24, 65535
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>
+}
+
+; Test a mixed vector (mask 0x8c76).
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgbm %v24, 35958
+; CHECK: br %r14
+  ret <2 x double> <double 0xff000000ffff0000, double 0x00ffffff00ffff00>
+}
+
+; Test that undefs are treated as zero (mask 0x8c00).
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgbm %v24, 35840
+; CHECK: br %r14
+  ret <2 x double> <double 0xff000000ffff0000, double undef>
+}
+
+; Test that we don't use VGBM if one of the bytes is not 0 or 0xff.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK-NOT: vgbm
+; CHECK: br %r14
+  ret <2 x double> <double 0xfe000000ffff0000, double 0x00ffffff00ffff00>
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-const-12.ll b/llvm/test/CodeGen/SystemZ/vec-const-12.ll
new file mode 100644
index 00000000000..ca66a3d173e
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-const-12.ll
@@ -0,0 +1,169 @@
+; Test vector replicates, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a byte-granularity replicate with the lowest useful value.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vrepib %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0101010101010101, double 0x0101010101010101>
+}
+
+; Test a byte-granularity replicate with an arbitrary value.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vrepib %v24, -55
+; CHECK: br %r14
+  ret <2 x double> <double 0xc9c9c9c9c9c9c9c9, double 0xc9c9c9c9c9c9c9c9>
+}
+
+; Test a byte-granularity replicate with the highest useful value.
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vrepib %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfefefefefefefefe, double 0xfefefefefefefefe>
+}
+
+; Test a halfword-granularity replicate with the lowest useful value.
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vrepih %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0001000100010001, double 0x0001000100010001>
+}
+
+; Test a halfword-granularity replicate with an arbitrary value.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vrepih %v24, 25650
+; CHECK: br %r14
+  ret <2 x double> <double 0x6432643264326432, double 0x6432643264326432>
+}
+
+; Test a halfword-granularity replicate with the highest useful value.
+define <2 x double> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vrepih %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffefffefffefffe, double 0xfffefffefffefffe>
+}
+
+; Test a word-granularity replicate with the lowest useful positive value.
+define <2 x double> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vrepif %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000100000001, double 0x0000000100000001>
+}
+
+; Test a word-granularity replicate with the highest in-range value.
+define <2 x double> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vrepif %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double 0x00007fff00007fff, double 0x00007fff00007fff>
+}
+
+; Test a word-granularity replicate with the next highest value.
+; This cannot use VREPIF.
+define <2 x double> @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000>
+}
+
+; Test a word-granularity replicate with the lowest in-range value.
+define <2 x double> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vrepif %v24, -32768
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff8000ffff8000, double 0xffff8000ffff8000>
+}
+
+; Test a word-granularity replicate with the next lowest value.
+; This cannot use VREPIF.
+define <2 x double> @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: vrepif
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff>
+}
+
+; Test a word-granularity replicate with the highest useful negative value.
+define <2 x double> @f12() {
+; CHECK-LABEL: f12:
+; CHECK: vrepif %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffefffffffe, double 0xfffffffefffffffe>
+}
+
+; Test a doubleword-granularity replicate with the lowest useful positive
+; value.
+define <2 x double> @f13() {
+; CHECK-LABEL: f13:
+; CHECK: vrepig %v24, 1
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000000001, double 0x0000000000000001>
+}
+
+; Test a doubleword-granularity replicate with the highest in-range value.
+define <2 x double> @f14() {
+; CHECK-LABEL: f14:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000007fff, double 0x0000000000007fff>
+}
+
+; Test a doubleword-granularity replicate with the next highest value.
+; This cannot use VREPIG.
+define <2 x double> @f15() {
+; CHECK-LABEL: f15:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000>
+}
+
+; Test a doubleword-granularity replicate with the lowest in-range value.
+define <2 x double> @f16() {
+; CHECK-LABEL: f16:
+; CHECK: vrepig %v24, -32768
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffff8000, double 0xffffffffffff8000>
+}
+
+; Test a doubleword-granularity replicate with the next lowest value.
+; This cannot use VREPIG.
+define <2 x double> @f17() {
+; CHECK-LABEL: f17:
+; CHECK-NOT: vrepig
+; CHECK: br %r14
+  ret <2 x double> <double 0xffffffffffff7fff, double 0xffffffffffff7fff>
+}
+
+; Test a doubleword-granularity replicate with the highest useful negative
+; value.
+define <2 x double> @f18() {
+; CHECK-LABEL: f18:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffffffffffe, double 0xfffffffffffffffe>
+}
+
+; Repeat f14 with undefs optimistically treated as 32767.
+define <2 x double> @f19() {
+; CHECK-LABEL: f19:
+; CHECK: vrepig %v24, 32767
+; CHECK: br %r14
+  ret <2 x double> <double undef, double 0x0000000000007fff>
+}
+
+; Repeat f18 with undefs optimistically treated as -2.
+define <2 x double> @f20() {
+; CHECK-LABEL: f20:
+; CHECK: vrepig %v24, -2
+; CHECK: br %r14
+  ret <2 x double> <double undef, double 0xfffffffffffffffe>
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-const-18.ll b/llvm/test/CodeGen/SystemZ/vec-const-18.ll
new file mode 100644
index 00000000000..c6c20c2a003
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-const-18.ll
@@ -0,0 +1,85 @@
+; Test vector replicates that use VECTOR GENERATE MASK, v2f64 version.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a word-granularity replicate with the lowest value that cannot use
+; VREPIF.
+define <2 x double> @f1() {
+; CHECK-LABEL: f1:
+; CHECK: vgmf %v24, 16, 16
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000800000008000, double 0x0000800000008000>
+}
+
+; Test a word-granularity replicate that has the lower 17 bits set.
+define <2 x double> @f2() {
+; CHECK-LABEL: f2:
+; CHECK: vgmf %v24, 15, 31
+; CHECK: br %r14
+  ret <2 x double> <double 0x0001ffff0001ffff, double 0x0001ffff0001ffff>
+}
+
+; Test a word-granularity replicate that has the upper 15 bits set.
+define <2 x double> @f3() {
+; CHECK-LABEL: f3:
+; CHECK: vgmf %v24, 0, 14
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffe0000fffe0000, double 0xfffe0000fffe0000>
+}
+
+; Test a word-granularity replicate that has middle bits set.
+define <2 x double> @f4() {
+; CHECK-LABEL: f4:
+; CHECK: vgmf %v24, 2, 11
+; CHECK: br %r14
+  ret <2 x double> <double 0x3ff000003ff00000, double 0x3ff000003ff00000>
+}
+
+; Test a word-granularity replicate with a wrap-around mask.
+define <2 x double> @f5() {
+; CHECK-LABEL: f5:
+; CHECK: vgmf %v24, 17, 15
+; CHECK: br %r14
+  ret <2 x double> <double 0xffff7fffffff7fff, double 0xffff7fffffff7fff>
+}
+
+; Test a doubleword-granularity replicate with the lowest value that cannot
+; use VREPIG.
+define <2 x double> @f6() {
+; CHECK-LABEL: f6:
+; CHECK: vgmg %v24, 48, 48
+; CHECK: br %r14
+  ret <2 x double> <double 0x0000000000008000, double 0x0000000000008000>
+}
+
+; Test a doubleword-granularity replicate that has the lower 22 bits set.
+define <2 x double> @f7() {
+; CHECK-LABEL: f7:
+; CHECK: vgmg %v24, 42, 63
+; CHECK: br %r14
+  ret <2 x double> <double 0x000000000003fffff, double 0x000000000003fffff>
+}
+
+; Test a doubleword-granularity replicate that has the upper 45 bits set.
+define <2 x double> @f8() {
+; CHECK-LABEL: f8:
+; CHECK: vgmg %v24, 0, 44
+; CHECK: br %r14
+  ret <2 x double> <double 0xfffffffffff80000, double 0xfffffffffff80000>
+}
+
+; Test a doubleword-granularity replicate that has middle bits set.
+define <2 x double> @f9() {
+; CHECK-LABEL: f9:
+; CHECK: vgmg %v24, 2, 11
+; CHECK: br %r14
+  ret <2 x double> <double 0x3ff0000000000000, double 0x3ff0000000000000>
+}
+
+; Test a doubleword-granularity replicate with a wrap-around mask.
+define <2 x double> @f10() {
+; CHECK-LABEL: f10:
+; CHECK: vgmg %v24, 10, 0
+; CHECK: br %r14
+  ret <2 x double> <double 0x803fffffffffffff, double 0x803fffffffffffff>
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-conv-01.ll b/llvm/test/CodeGen/SystemZ/vec-conv-01.ll
new file mode 100644
index 00000000000..cbf42c0f533
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-conv-01.ll
@@ -0,0 +1,95 @@
+; Test conversions between integer and float elements.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test conversion of f64s to signed i64s.
+define <2 x i64> @f1(<2 x double> %doubles) {
+; CHECK-LABEL: f1:
+; CHECK: vcgdb %v24, %v24, 0, 5
+; CHECK: br %r14
+  %dwords = fptosi <2 x double> %doubles to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of f64s to unsigned i64s.
+define <2 x i64> @f2(<2 x double> %doubles) {
+; CHECK-LABEL: f2:
+; CHECK: vclgdb %v24, %v24, 0, 5
+; CHECK: br %r14
+  %dwords = fptoui <2 x double> %doubles to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of signed i64s to f64s.
+define <2 x double> @f3(<2 x i64> %dwords) {
+; CHECK-LABEL: f3:
+; CHECK: vcdgb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %doubles = sitofp <2 x i64> %dwords to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of unsigned i64s to f64s.
+define <2 x double> @f4(<2 x i64> %dwords) {
+; CHECK-LABEL: f4:
+; CHECK: vcdlgb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %doubles = uitofp <2 x i64> %dwords to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of f64s to signed i32s, which must compile.
+define void @f5(<2 x double> %doubles, <2 x i32> *%ptr) {
+  %words = fptosi <2 x double> %doubles to <2 x i32>
+  store <2 x i32> %words, <2 x i32> *%ptr
+  ret void
+}
+
+; Test conversion of f64s to unsigned i32s, which must compile.
+define void @f6(<2 x double> %doubles, <2 x i32> *%ptr) {
+  %words = fptoui <2 x double> %doubles to <2 x i32>
+  store <2 x i32> %words, <2 x i32> *%ptr
+  ret void
+}
+
+; Test conversion of signed i32s to f64s, which must compile.
+define <2 x double> @f7(<2 x i32> *%ptr) {
+  %words = load <2 x i32>, <2 x i32> *%ptr
+  %doubles = sitofp <2 x i32> %words to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of unsigned i32s to f64s, which must compile.
+define <2 x double> @f8(<2 x i32> *%ptr) {
+  %words = load <2 x i32>, <2 x i32> *%ptr
+  %doubles = uitofp <2 x i32> %words to <2 x double>
+  ret <2 x double> %doubles
+}
+
+; Test conversion of f32s to signed i64s, which must compile.
+define <2 x i64> @f9(<2 x float> *%ptr) {
+  %floats = load <2 x float>, <2 x float> *%ptr
+  %dwords = fptosi <2 x float> %floats to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of f32s to unsigned i64s, which must compile.
+define <2 x i64> @f10(<2 x float> *%ptr) {
+  %floats = load <2 x float>, <2 x float> *%ptr
+  %dwords = fptoui <2 x float> %floats to <2 x i64>
+  ret <2 x i64> %dwords
+}
+
+; Test conversion of signed i64s to f32, which must compile.
+define void @f11(<2 x i64> %dwords, <2 x float> *%ptr) {
+  %floats = sitofp <2 x i64> %dwords to <2 x float>
+  store <2 x float> %floats, <2 x float> *%ptr
+  ret void
+}
+
+; Test conversion of unsigned i64s to f32, which must compile.
+define void @f12(<2 x i64> %dwords, <2 x float> *%ptr) {
+  %floats = uitofp <2 x i64> %dwords to <2 x float>
+  store <2 x float> %floats, <2 x float> *%ptr
+  ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-div-01.ll b/llvm/test/CodeGen/SystemZ/vec-div-01.ll
index 3c5ec4f54ee..5666444e9da 100644
--- a/llvm/test/CodeGen/SystemZ/vec-div-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-div-01.ll
@@ -1,5 +1,5 @@
-; Test vector division.  There is no native support for this, so it's really
-; a test of the operation legalization code.
+; Test vector division.  There is no native integer support for this,
+; so the integer cases are really a test of the operation legalization code.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
@@ -60,3 +60,13 @@ define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
   %ret = sdiv <2 x i64> %val1, %val2
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 division.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfddb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fdiv <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-log-01.ll b/llvm/test/CodeGen/SystemZ/vec-log-01.ll
new file mode 100644
index 00000000000..f9b7402f08e
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-log-01.ll
@@ -0,0 +1,15 @@
+; Test v2f64 logarithm.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.log.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: brasl %r14, log@PLT
+; CHECK: brasl %r14, log@PLT
+; CHECK: vmrhg %v24,
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.log.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-01.ll b/llvm/test/CodeGen/SystemZ/vec-move-01.ll
index 952e5a42126..f9ae13b3ba1 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-01.ll
@@ -33,3 +33,11 @@ define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
 ; CHECK: br %r14
   ret <2 x i64> %val2
 }
+
+; Test v2f64 moves.
+define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+  ret <2 x double> %val2
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-02.ll b/llvm/test/CodeGen/SystemZ/vec-move-02.ll
index b7b3ab6798d..a8c6912f0c7 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-02.ll
@@ -38,6 +38,15 @@ define <2 x i64> @f4(<2 x i64> *%ptr) {
   ret <2 x i64> %ret
 }
 
+; Test v2f64 loads.
+define <2 x double> @f6(<2 x double> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vl %v24, 0(%r2)
+; CHECK: br %r14
+  %ret = load <2 x double>, <2 x double> *%ptr
+  ret <2 x double> %ret
+}
+
 ; Test the highest aligned in-range offset.
 define <16 x i8> @f7(<16 x i8> *%base) {
 ; CHECK-LABEL: f7:
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-03.ll b/llvm/test/CodeGen/SystemZ/vec-move-03.ll
index ddce4ef209a..abd7c939fbe 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-03.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-03.ll
@@ -38,6 +38,15 @@ define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
   ret void
 }
 
+; Test v2f64 stores.
+define void @f6(<2 x double> %val, <2 x double> *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK: vst %v24, 0(%r2)
+; CHECK: br %r14
+  store <2 x double> %val, <2 x double> *%ptr
+  ret void
+}
+
 ; Test the highest aligned in-range offset.
 define void @f7(<16 x i8> %val, <16 x i8> *%base) {
 ; CHECK-LABEL: f7:
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-04.ll b/llvm/test/CodeGen/SystemZ/vec-move-04.ll
index f43c0b71491..4e75d21dc96 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-04.ll
@@ -110,6 +110,34 @@ define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) {
   ret <2 x i64> %ret
 }
 
+; Test v2f64 insertion into the first element.
+define <2 x double> @f16(<2 x double> %val, double %element) {
+; CHECK-LABEL: f16:
+; CHECK: vpdi %v24, %v0, %v24, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into the last element.
+define <2 x double> @f17(<2 x double> %val, double %element) {
+; CHECK-LABEL: f17:
+; CHECK: vpdi %v24, %v24, %v0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into a variable element.
+define <2 x double> @f18(<2 x double> %val, double %element, i32 %index) {
+; CHECK-LABEL: f18:
+; CHECK: lgdr [[REG:%r[0-5]]], %f0
+; CHECK: vlvgg %v24, [[REG]], 0(%r2)
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double %element, i32 %index
+  ret <2 x double> %ret
+}
+
 ; Test v16i8 insertion into a variable element plus one.
 define <16 x i8> @f19(<16 x i8> %val, i8 %element, i32 %index) {
 ; CHECK-LABEL: f19:
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-05.ll b/llvm/test/CodeGen/SystemZ/vec-move-05.ll
index 60a0666c2f9..234157a0abb 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-05.ll
@@ -150,6 +150,41 @@ define i64 @f16(<2 x i64> %val, i32 %index) {
   ret i64 %ret
 }
 
+; Test v2f64 extraction of the first element.
+define double @f23(<2 x double> %val) {
+; CHECK-LABEL: f23:
+; CHECK: vlr %v0, %v24
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 0
+  ret double %ret
+}
+
+; Test v2f64 extraction of the last element.
+define double @f24(<2 x double> %val) {
+; CHECK-LABEL: f24:
+; CHECK: vrepg %v0, %v24, 1
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 1
+  ret double %ret
+}
+
+; Test v2f64 extractions of an absurd element number.  This must compile
+; but we don't care what it does.
+define double @f25(<2 x double> %val) {
+  %ret = extractelement <2 x double> %val, i32 100000
+  ret double %ret
+}
+
+; Test v2f64 extraction of a variable element.
+define double @f26(<2 x double> %val, i32 %index) {
+; CHECK-LABEL: f26:
+; CHECK: vlgvg [[REG:%r[0-5]]], %v24, 0(%r2)
+; CHECK: ldgr %f0, [[REG]]
+; CHECK: br %r14
+  %ret = extractelement <2 x double> %val, i32 %index
+  ret double %ret
+}
+
 ; Test v16i8 extraction of a variable element with an offset.
 define i8 @f27(<16 x i8> %val, i32 %index) {
 ; CHECK-LABEL: f27:
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-07.ll b/llvm/test/CodeGen/SystemZ/vec-move-07.ll
index a688b089b97..0cb8a0a1dfc 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-07.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-07.ll
@@ -37,3 +37,12 @@ define <2 x i64> @f4(i64 %val) {
   %ret = insertelement <2 x i64> undef, i64 %val, i32 0
   ret <2 x i64> %ret
 }
+
+; Test v2f64, which is just a move.
+define <2 x double> @f6(double %val) {
+; CHECK-LABEL: f6:
+; CHECK: vlr %v24, %v0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> undef, double %val, i32 0
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-08.ll b/llvm/test/CodeGen/SystemZ/vec-move-08.ll
index 94a3b3aefba..6148529c225 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-08.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-08.ll
@@ -214,6 +214,59 @@ define <2 x i64> @f20(<2 x i64> %val, i64 *%ptr, i32 %index) {
   ret <2 x i64> %ret
 }
 
+; Test v2f64 insertion into the first element.
+define <2 x double> @f26(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f26:
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into the last element.
+define <2 x double> @f27(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f27:
+; CHECK: vleg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion with the highest in-range offset.
+define <2 x double> @f28(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f28:
+; CHECK: vleg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion with the first ouf-of-range offset.
+define <2 x double> @f29(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f29:
+; CHECK: aghi %r2, 4096
+; CHECK: vleg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion into a variable element.
+define <2 x double> @f30(<2 x double> %val, double *%ptr, i32 %index) {
+; CHECK-LABEL: f30:
+; CHECK-NOT: vleg
+; CHECK: br %r14
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 %index
+  ret <2 x double> %ret
+}
+
 ; Test a v4i32 gather of the first element.
 define <4 x i32> @f31(<4 x i32> %val, <4 x i32> %index, i64 %base) {
 ; CHECK-LABEL: f31:
@@ -282,3 +335,29 @@ define <2 x i64> @f35(<2 x i64> %val, <2 x i64> %index, i64 %base) {
   %ret = insertelement <2 x i64> %val, i64 %element, i32 1
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 gather of the first element.
+define <2 x double> @f38(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f38:
+; CHECK: vgeg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 0
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 gather of the last element.
+define <2 x double> @f39(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f39:
+; CHECK: vgeg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = load double, double *%ptr
+  %ret = insertelement <2 x double> %val, double %element, i32 1
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-09.ll b/llvm/test/CodeGen/SystemZ/vec-move-09.ll
index 7863e4305f9..78c5454fb55 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-09.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-09.ll
@@ -235,3 +235,30 @@ define <2 x i64> @f26(<2 x i64> %val, i32 %index) {
   %ret = insertelement <2 x i64> %val, i64 0, i32 %index
   ret <2 x i64> %ret
 }
+
+; Test v2f64 insertion of 0 into the first element.
+define <2 x double> @f30(<2 x double> %val) {
+; CHECK-LABEL: f30:
+; CHECK: vleig %v24, 0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 0.0, i32 0
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion of 0 into the last element.
+define <2 x double> @f31(<2 x double> %val) {
+; CHECK-LABEL: f31:
+; CHECK: vleig %v24, 0, 1
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 0.0, i32 1
+  ret <2 x double> %ret
+}
+
+; Test v2f64 insertion of a nonzero value.
+define <2 x double> @f32(<2 x double> %val) {
+; CHECK-LABEL: f32:
+; CHECK-NOT: vleig
+; CHECK: br %r14
+  %ret = insertelement <2 x double> %val, double 1.0, i32 1
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-10.ll b/llvm/test/CodeGen/SystemZ/vec-move-10.ll
index 852a4a7c4ed..bc854214bbd 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-10.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-10.ll
@@ -258,6 +258,59 @@ define void @f24(<2 x i64> %val, i64 *%ptr, i32 %index) {
   ret void
 }
 
+; Test v2f64 extraction from the first element.
+define void @f32(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f32:
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction from the last element.
+define void @f33(<2 x double> %val, double *%ptr) {
+; CHECK-LABEL: f33:
+; CHECK: vsteg %v24, 0(%r2), 1
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction with the highest in-range offset.
+define void @f34(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f34:
+; CHECK: vsteg %v24, 4088(%r2), 1
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction with the first ouf-of-range offset.
+define void @f35(<2 x double> %val, double *%base) {
+; CHECK-LABEL: f35:
+; CHECK: aghi %r2, 4096
+; CHECK: vsteg %v24, 0(%r2), 0
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test v2f64 extraction from a variable element.
+define void @f36(<2 x double> %val, double *%ptr, i32 %index) {
+; CHECK-LABEL: f36:
+; CHECK-NOT: vsteg
+; CHECK: br %r14
+  %element = extractelement <2 x double> %val, i32 %index
+  store double %element, double *%ptr
+  ret void
+}
+
 ; Test a v4i32 scatter of the first element.
 define void @f37(<4 x i32> %val, <4 x i32> %index, i64 %base) {
 ; CHECK-LABEL: f37:
@@ -326,3 +379,29 @@ define void @f41(<2 x i64> %val, <2 x i64> %index, i64 %base) {
   store i64 %element, i64 *%ptr
   ret void
 }
+
+; Test a v2f64 scatter of the first element.
+define void @f44(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f44:
+; CHECK: vsceg %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 0
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = extractelement <2 x double> %val, i32 0
+  store double %element, double *%ptr
+  ret void
+}
+
+; Test a v2f64 scatter of the last element.
+define void @f45(<2 x double> %val, <2 x i64> %index, i64 %base) {
+; CHECK-LABEL: f45:
+; CHECK: vsceg %v24, 0(%v26,%r2), 1
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to double *
+  %element = extractelement <2 x double> %val, i32 1
+  store double %element, double *%ptr
+  ret void
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-11.ll b/llvm/test/CodeGen/SystemZ/vec-move-11.ll
index 45bc91b169b..07a037ccdf2 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-11.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-11.ll
@@ -91,3 +91,12 @@ define <2 x i64> @f10(i64 %val) {
   %ret = insertelement <2 x i64> undef, i64 %val, i32 1
   ret <2 x i64> %ret
 }
+
+; Test v2f64 insertion into an undef.
+define <2 x double> @f12(double %val) {
+; CHECK-LABEL: f12:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> undef, double %val, i32 1
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-12.ll b/llvm/test/CodeGen/SystemZ/vec-move-12.ll
index 1fecab688e7..94b186f46e5 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-12.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-12.ll
@@ -101,3 +101,13 @@ define <2 x i64> @f10(i64 *%ptr) {
   %ret = insertelement <2 x i64> undef, i64 %val, i32 1
   ret <2 x i64> %ret
 }
+
+; Test v2f64 insertion into an undef.
+define <2 x double> @f12(double *%ptr) {
+; CHECK-LABEL: f12:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load double, double *%ptr
+  %ret = insertelement <2 x double> undef, double %val, i32 1
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-13.ll b/llvm/test/CodeGen/SystemZ/vec-move-13.ll
index e103affa4b1..c50c94afb6c 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-13.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-13.ll
@@ -45,3 +45,13 @@ define <2 x i64> @f4(i64 %val) {
   %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 1
   ret <2 x i64> %ret
 }
+
+; Test v2f64 insertion into 0.
+define <2 x double> @f6(double %val) {
+; CHECK-LABEL: f6:
+; CHECK: vgbm [[REG:%v[0-9]+]], 0
+; CHECK: vmrhg %v24, [[REG]], %v0
+; CHECK: br %r14
+  %ret = insertelement <2 x double> zeroinitializer, double %val, i32 1
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-14.ll b/llvm/test/CodeGen/SystemZ/vec-move-14.ll
index f0c60e7d366..b48f2175ebe 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-14.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-14.ll
@@ -74,3 +74,13 @@ define <2 x i64> @f7(i64 *%ptr) {
   %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 0
   ret <2 x i64> %ret
 }
+
+; Test VLLEZG with a double.
+define <2 x double> @f9(double *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: vllezg %v24, 0(%r2)
+; CHECK: br %r14
+  %val = load double, double *%ptr
+  %ret = insertelement <2 x double> zeroinitializer, double %val, i32 0
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-mul-01.ll b/llvm/test/CodeGen/SystemZ/vec-mul-01.ll
index 209582f5893..d0018fa1f8c 100644
--- a/llvm/test/CodeGen/SystemZ/vec-mul-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-mul-01.ll
@@ -37,3 +37,13 @@ define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
   %ret = mul <2 x i64> %val1, %val2
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 multiplication.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vfmdb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fmul <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-mul-02.ll b/llvm/test/CodeGen/SystemZ/vec-mul-02.ll
index 7323330919a..11a651e4997 100644
--- a/llvm/test/CodeGen/SystemZ/vec-mul-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-mul-02.ll
@@ -2,6 +2,8 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
+declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
+
 ; Test a v16i8 multiply-and-add.
 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2,
                      <16 x i8> %val3) {
@@ -34,3 +36,28 @@ define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2,
   %ret = add <4 x i32> %mul, %val3
   ret <4 x i32> %ret
 }
+
+; Test a v2f64 multiply-and-add.
+define <2 x double> @f4(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2, <2 x double> %val3) {
+; CHECK-LABEL: f4:
+; CHECK: vfmadb %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1,
+                                            <2 x double> %val2,
+                                            <2 x double> %val3)
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 multiply-and-subtract.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2, <2 x double> %val3) {
+; CHECK-LABEL: f5:
+; CHECK: vfmsdb %v24, %v26, %v28, %v30
+; CHECK: br %r14
+  %negval3 = fsub <2 x double> <double -0.0, double -0.0>, %val3
+  %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1,
+                                            <2 x double> %val2,
+                                            <2 x double> %negval3)
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-neg-01.ll b/llvm/test/CodeGen/SystemZ/vec-neg-01.ll
index 357648ba4d3..491e24bb34f 100644
--- a/llvm/test/CodeGen/SystemZ/vec-neg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-neg-01.ll
@@ -37,3 +37,12 @@ define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val) {
   %ret = sub <2 x i64> zeroinitializer, %val
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 negation.
+define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vflcdb %v24, %v26
+; CHECK: br %r14
+  %ret = fsub <2 x double> <double -0.0, double -0.0>, %val
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-01.ll b/llvm/test/CodeGen/SystemZ/vec-perm-01.ll
index 520ff45e7f7..c68958a98a2 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-01.ll
@@ -122,3 +122,23 @@ define <2 x i64> @f11(<2 x i64> %val) {
                        <2 x i32> <i32 1, i32 1>
   ret <2 x i64> %ret
 }
+
+; Test v2f64 splat of the first element.
+define <2 x double> @f15(<2 x double> %val) {
+; CHECK-LABEL: f15:
+; CHECK: vrepg %v24, %v24, 0
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test v2f64 splat of the last element.
+define <2 x double> @f16(<2 x double> %val) {
+; CHECK-LABEL: f16:
+; CHECK: vrepg %v24, %v24, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-02.ll b/llvm/test/CodeGen/SystemZ/vec-perm-02.ll
index 93e4112c0ef..7158990174b 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-02.ll
@@ -142,3 +142,25 @@ define <2 x i64> @f11(i64 %scalar) {
                        <2 x i32> <i32 1, i32 1>
   ret <2 x i64> %ret
 }
+
+; Test v2f64 splat of the first element.
+define <2 x double> @f15(double %scalar) {
+; CHECK-LABEL: f15:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test v2f64 splat of the last element.
+define <2 x double> @f16(double %scalar) {
+; CHECK-LABEL: f16:
+; CHECK: vrepg %v24, %v0, 0
+; CHECK: br %r14
+  %val = insertelement <2 x double> undef, double %scalar, i32 1
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> <i32 1, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-03.ll b/llvm/test/CodeGen/SystemZ/vec-perm-03.ll
index d74948bdb51..c30a87601a4 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-03.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-03.ll
@@ -158,6 +158,46 @@ define <2 x i64> @f12(i64 *%base) {
   ret <2 x i64> %ret
 }
 
+
+; Test a v2f64 replicating load with no offset.
+define <2 x double> @f16(double *%ptr) {
+; CHECK-LABEL: f16:
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 replicating load with the maximum in-range offset.
+define <2 x double> @f17(double *%base) {
+; CHECK-LABEL: f17:
+; CHECK: vlrepg %v24, 4088(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 511
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
+; Test a v2f64 replicating load with the first out-of-range offset.
+define <2 x double> @f18(double *%base) {
+; CHECK-LABEL: f18:
+; CHECK: aghi %r2, 4096
+; CHECK: vlrepg %v24, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr double, double *%base, i32 512
+  %scalar = load double, double *%ptr
+  %val = insertelement <2 x double> undef, double %scalar, i32 0
+  %ret = shufflevector <2 x double> %val, <2 x double> undef,
+                       <2 x i32> zeroinitializer
+  ret <2 x double> %ret
+}
+
 ; Test a v16i8 replicating load with an index.
 define <16 x i8> @f19(i8 *%base, i64 %index) {
 ; CHECK-LABEL: f19:
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-04.ll b/llvm/test/CodeGen/SystemZ/vec-perm-04.ll
index 1d449b9bb34..ca04fdf6913 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-04.ll
@@ -158,3 +158,23 @@ define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
                        <2 x i32> <i32 2, i32 0>
   ret <2 x i64> %ret
 }
+
+; Test a canonical v2f64 merge high.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f16:
+; CHECK: vmrhg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 0, i32 2>
+  ret <2 x double> %ret
+}
+
+; Test a reversed v2f64 merge high.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f17:
+; CHECK: vmrhg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 2, i32 0>
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-05.ll b/llvm/test/CodeGen/SystemZ/vec-perm-05.ll
index 636228c56ba..f4a46ff4e27 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-05.ll
@@ -158,3 +158,23 @@ define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
                        <2 x i32> <i32 3, i32 1>
   ret <2 x i64> %ret
 }
+
+; Test a canonical v2f64 merge low.
+define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f16:
+; CHECK: vmrlg %v24, %v24, %v26
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 1, i32 3>
+  ret <2 x double> %ret
+}
+
+; Test a reversed v2f64 merge low.
+define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f17:
+; CHECK: vmrlg %v24, %v26, %v24
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 3, i32 1>
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-08.ll b/llvm/test/CodeGen/SystemZ/vec-perm-08.ll
index 4d06377f5a3..b5220ab6712 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-08.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-08.ll
@@ -128,3 +128,23 @@ define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2) {
                        <2 x i32> <i32 3, i32 0>
   ret <2 x i64> %ret
 }
+
+; Test a high1/low2 permute for v2f64.
+define <2 x double> @f14(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f14:
+; CHECK: vpdi %v24, %v24, %v26, 1
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 0, i32 3>
+  ret <2 x double> %ret
+}
+
+; Test a low2/high1 permute for v2f64.
+define <2 x double> @f15(<2 x double> %val1, <2 x double> %val2) {
+; CHECK-LABEL: f15:
+; CHECK: vpdi %v24, %v26, %v24, 4
+; CHECK: br %r14
+  %ret = shufflevector <2 x double> %val1, <2 x double> %val2,
+                       <2 x i32> <i32 3, i32 0>
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-round-01.ll b/llvm/test/CodeGen/SystemZ/vec-round-01.ll
new file mode 100644
index 00000000000..284b83e96f7
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-round-01.ll
@@ -0,0 +1,58 @@
+; Test v2f64 rounding.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.rint.v2f64(<2 x double>)
+declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)
+declare <2 x double> @llvm.floor.v2f64(<2 x double>)
+declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
+declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
+declare <2 x double> @llvm.round.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vfidb %v24, %v24, 0, 0
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f2(<2 x double> %val) {
+; CHECK-LABEL: f2:
+; CHECK: vfidb %v24, %v24, 4, 0
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f3(<2 x double> %val) {
+; CHECK-LABEL: f3:
+; CHECK: vfidb %v24, %v24, 4, 7
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f4(<2 x double> %val) {
+; CHECK-LABEL: f4:
+; CHECK: vfidb %v24, %v24, 4, 6
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.ceil.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f5(<2 x double> %val) {
+; CHECK-LABEL: f5:
+; CHECK: vfidb %v24, %v24, 4, 5
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.trunc.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
+
+define <2 x double> @f6(<2 x double> %val) {
+; CHECK-LABEL: f6:
+; CHECK: vfidb %v24, %v24, 4, 1
+; CHECK: br %r14
+  %res = call <2 x double> @llvm.round.v2f64(<2 x double> %val)
+  ret <2 x double> %res
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-sqrt-01.ll b/llvm/test/CodeGen/SystemZ/vec-sqrt-01.ll
new file mode 100644
index 00000000000..0160c24a749
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/vec-sqrt-01.ll
@@ -0,0 +1,13 @@
+; Test v2f64 square root.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+declare <2 x double> @llvm.sqrt.v2f64(<2 x double>)
+
+define <2 x double> @f1(<2 x double> %val) {
+; CHECK-LABEL: f1:
+; CHECK: vfsqdb %v24, %v24
+; CHECK: br %r14
+  %ret = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %val)
+  ret <2 x double> %ret
+}
diff --git a/llvm/test/CodeGen/SystemZ/vec-sub-01.ll b/llvm/test/CodeGen/SystemZ/vec-sub-01.ll
index 9e5b4f81e6d..24d4ba5a2bd 100644
--- a/llvm/test/CodeGen/SystemZ/vec-sub-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-sub-01.ll
@@ -37,3 +37,13 @@ define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
   %ret = sub <2 x i64> %val1, %val2
   ret <2 x i64> %ret
 }
+
+; Test a v2f64 subtraction.
+define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
+                        <2 x double> %val2) {
+; CHECK-LABEL: f6:
+; CHECK: vfsdb %v24, %v26, %v28
+; CHECK: br %r14
+  %ret = fsub <2 x double> %val1, %val2
+  ret <2 x double> %ret
+}