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| author | Cameron McInally <cameron.mcinally@nyu.edu> | 2018-11-13 18:15:47 +0000 |
|---|---|---|
| committer | Cameron McInally <cameron.mcinally@nyu.edu> | 2018-11-13 18:15:47 +0000 |
| commit | cbde0d9c7be1991751dc3eb5928294d2e00ef26a (patch) | |
| tree | ad839084df9863182687fadb95471920cb15381b /llvm/test/CodeGen | |
| parent | 9d87256d3de67f7a2e8f778ee775e0b6bb309aeb (diff) | |
| download | bcm5719-llvm-cbde0d9c7be1991751dc3eb5928294d2e00ef26a.tar.gz bcm5719-llvm-cbde0d9c7be1991751dc3eb5928294d2e00ef26a.zip | |
[IR] Add a dedicated FNeg IR Instruction
The IEEE-754 Standard makes it clear that fneg(x) and
fsub(-0.0, x) are two different operations. The former is a bitwise
operation, while the latter is an arithmetic operation. This patch
creates a dedicated FNeg IR Instruction to model that behavior.
Differential Revision: https://reviews.llvm.org/D53877
llvm-svn: 346774
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Generic/fneg-fabs.ll | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_fneg.ll | 15 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Generic/fneg-fabs.ll b/llvm/test/CodeGen/Generic/fneg-fabs.ll index 2f2f59762cb..cafc1f132b5 100644 --- a/llvm/test/CodeGen/Generic/fneg-fabs.ll +++ b/llvm/test/CodeGen/Generic/fneg-fabs.ll @@ -10,6 +10,21 @@ define float @fnegf(float %X) { ret float %Y } +define double @real_fneg(double %X) { + %Y = fneg double %X ; <double> [#uses=1] + ret double %Y +} + +define double @real_fneg_constant() { + %Y = fneg double -2.0 ; <double> [#uses=1] + ret double %Y +} + +define float @real_fnegf(float %X) { + %Y = fneg float %X ; <float> [#uses=1] + ret float %Y +} + declare double @fabs(double) declare float @fabsf(float) diff --git a/llvm/test/CodeGen/X86/vec_fneg.ll b/llvm/test/CodeGen/X86/vec_fneg.ll index e84f7163bbe..f0c98990683 100644 --- a/llvm/test/CodeGen/X86/vec_fneg.ll +++ b/llvm/test/CodeGen/X86/vec_fneg.ll @@ -127,3 +127,18 @@ define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) { ret <4 x float> %r } +define <4 x float> @fneg(<4 x float> %Q) nounwind { +; X32-SSE-LABEL: fneg: +; X32-SSE: # %bb.0: +; X32-SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0 +; X32-SSE-NEXT: retl +; +; X64-SSE-LABEL: fneg: +; X64-SSE: # %bb.0: +; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0 +; X64-SSE-NEXT: retq + %tmp = fneg <4 x float> %Q + ret <4 x float> %tmp +} + + |

