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| author | Craig Topper <craig.topper@intel.com> | 2019-03-14 16:53:24 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-03-14 16:53:24 +0000 |
| commit | c747ac3f936adbccdcb7ee64a64961b33344b5ec (patch) | |
| tree | abc4e9362340f7023a1801decbd31cb09c9285b8 /llvm/test/CodeGen | |
| parent | e69917f16624d3d3531753a02291a6da9ef4befb (diff) | |
| download | bcm5719-llvm-c747ac3f936adbccdcb7ee64a64961b33344b5ec.tar.gz bcm5719-llvm-c747ac3f936adbccdcb7ee64a64961b33344b5ec.zip | |
[X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode.
These instructions used to use rotl with a bitwidth-1 immediate. I changed the immediate to 1,
but failed to change the opcode.
Thankfully this seems to have not caused a functional issue because we now had two rotl by 1 patterns,
but the correct ones were earlier and took priority. So we just missed some optimization.
llvm-svn: 356164
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/funnel-shift-rot.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/rot32.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/rot64.ll | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/funnel-shift-rot.ll b/llvm/test/CodeGen/X86/funnel-shift-rot.ll index 29e1b3e065b..b5e17ab8020 100644 --- a/llvm/test/CodeGen/X86/funnel-shift-rot.ll +++ b/llvm/test/CodeGen/X86/funnel-shift-rot.ll @@ -205,13 +205,13 @@ define i8 @rotr_i8_const_shift1(i8 %x) nounwind { ; X32-SSE2-LABEL: rotr_i8_const_shift1: ; X32-SSE2: # %bb.0: ; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al -; X32-SSE2-NEXT: rorb $1, %al +; X32-SSE2-NEXT: rorb %al ; X32-SSE2-NEXT: retl ; ; X64-AVX2-LABEL: rotr_i8_const_shift1: ; X64-AVX2: # %bb.0: ; X64-AVX2-NEXT: movl %edi, %eax -; X64-AVX2-NEXT: rorb $1, %al +; X64-AVX2-NEXT: rorb %al ; X64-AVX2-NEXT: # kill: def $al killed $al killed $eax ; X64-AVX2-NEXT: retq %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 1) diff --git a/llvm/test/CodeGen/X86/rot32.ll b/llvm/test/CodeGen/X86/rot32.ll index d6c5ae22139..29dd679ae9d 100644 --- a/llvm/test/CodeGen/X86/rot32.ll +++ b/llvm/test/CodeGen/X86/rot32.ll @@ -514,7 +514,7 @@ define i32 @fshr1(i32 %x) nounwind { ; X86-LABEL: fshr1: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: rorl $1, %eax +; X86-NEXT: rorl %eax ; X86-NEXT: retl ; ; SHLD-LABEL: fshr1: @@ -531,7 +531,7 @@ define i32 @fshr1(i32 %x) nounwind { ; X64-LABEL: fshr1: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: rorl $1, %eax +; X64-NEXT: rorl %eax ; X64-NEXT: retq ; ; SHLD64-LABEL: fshr1: diff --git a/llvm/test/CodeGen/X86/rot64.ll b/llvm/test/CodeGen/X86/rot64.ll index 43ece70ad36..fdc7e9ab21a 100644 --- a/llvm/test/CodeGen/X86/rot64.ll +++ b/llvm/test/CodeGen/X86/rot64.ll @@ -303,7 +303,7 @@ define i64 @fshr1(i64 %x) nounwind { ; X64-LABEL: fshr1: ; X64: # %bb.0: ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: rorq $1, %rax +; X64-NEXT: rorq %rax ; X64-NEXT: retq ; ; SHLD-LABEL: fshr1: |
