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authorHrvoje Varga <Hrvoje.Varga@imgtec.com>2016-04-25 15:40:08 +0000
committerHrvoje Varga <Hrvoje.Varga@imgtec.com>2016-04-25 15:40:08 +0000
commitc2dd5d223ac0c5a1cdc113e23c13cbf3252a70b4 (patch)
tree78f40ff7e7faf0107a124a046278b7246a22d7ae /llvm/test/CodeGen
parentb43d4bcbd5be9705f404197bcf3c55cf8097e556 (diff)
downloadbcm5719-llvm-c2dd5d223ac0c5a1cdc113e23c13cbf3252a70b4.tar.gz
bcm5719-llvm-c2dd5d223ac0c5a1cdc113e23c13cbf3252a70b4.zip
[mips][microMIPS] Revert commit r267137
Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/Mips/brconlt.ll2
-rw-r--r--llvm/test/CodeGen/Mips/seteq.ll2
-rw-r--r--llvm/test/CodeGen/Mips/setltk.ll6
-rw-r--r--llvm/test/CodeGen/Mips/setne.ll2
4 files changed, 2 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll
index 3fc937d4ec8..487018c22f2 100644
--- a/llvm/test/CodeGen/Mips/brconlt.ll
+++ b/llvm/test/CodeGen/Mips/brconlt.ll
@@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@i = global i32 5, align 4
@j = global i32 10, align 4
@@ -14,7 +13,6 @@ entry:
br i1 %cmp, label %if.end, label %if.then
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
; 16: $[[LABEL]]:
diff --git a/llvm/test/CodeGen/Mips/seteq.ll b/llvm/test/CodeGen/Mips/seteq.ll
index 532dd3b311f..76f9bb3ebf9 100644
--- a/llvm/test/CodeGen/Mips/seteq.ll
+++ b/llvm/test/CodeGen/Mips/seteq.ll
@@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -16,7 +15,6 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
; 16: move ${{[0-9]+}}, $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setltk.ll b/llvm/test/CodeGen/Mips/setltk.ll
index 32414afd365..79d25b1f130 100644
--- a/llvm/test/CodeGen/Mips/setltk.ll
+++ b/llvm/test/CodeGen/Mips/setltk.ll
@@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -15,8 +14,7 @@ entry:
%cmp = icmp slt i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slti $[[REGISTER:[0-9]+]], 10
-; MM32R6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
-; 16: move $[[REGISTER]], $24
+; 16: slti $[[REGISTER:[0-9]+]], 10
+; 16: move $[[REGISTER]], $24
ret void
}
diff --git a/llvm/test/CodeGen/Mips/setne.ll b/llvm/test/CodeGen/Mips/setne.ll
index 9b0e6e65fca..02692bf9e63 100644
--- a/llvm/test/CodeGen/Mips/setne.ll
+++ b/llvm/test/CodeGen/Mips/setne.ll
@@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -16,7 +15,6 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
-; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}}
; 16: move ${{[0-9]+}}, $24
ret void
}
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