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authorAlex Bradbury <asb@lowrisc.org>2018-05-11 17:30:28 +0000
committerAlex Bradbury <asb@lowrisc.org>2018-05-11 17:30:28 +0000
commitbca0c3cdb6d49822dbfbcac0bd2719e17e08f309 (patch)
tree7304ed476ecdabf44c65567bd77fde8a98deb0b3 /llvm/test/CodeGen
parent0d7c37756bc3609d9a1f3a9d9ba79842acca1e4a (diff)
downloadbcm5719-llvm-bca0c3cdb6d49822dbfbcac0bd2719e17e08f309.tar.gz
bcm5719-llvm-bca0c3cdb6d49822dbfbcac0bd2719e17e08f309.zip
[RISCV] Support .option rvc and norvc assembler directives
These directives allow the 'C' (compressed) extension to be enabled/disabled within a single file. Differential Revision: https://reviews.llvm.org/D45864 Patch by Kito Cheng llvm-svn: 332107
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/RISCV/option-norvc.ll15
-rw-r--r--llvm/test/CodeGen/RISCV/option-rvc.ll15
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/option-norvc.ll b/llvm/test/CodeGen/RISCV/option-norvc.ll
new file mode 100644
index 00000000000..381fb37735d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/option-norvc.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s\
+; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -riscv-no-aliases -\
+; RUN: | FileCheck -check-prefix=CHECK %s
+
+; This test demonstrates that .option norvc has no effect on codegen when
+; emitting an ELF directly.
+
+define i32 @add(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: add:
+; CHECK: c.add a0, a1
+; CHECK-NEXT: c.jr ra
+ tail call void asm sideeffect ".option norvc", ""()
+ %add = add nsw i32 %b, %a
+ ret i32 %add
+}
diff --git a/llvm/test/CodeGen/RISCV/option-rvc.ll b/llvm/test/CodeGen/RISCV/option-rvc.ll
new file mode 100644
index 00000000000..3c207bd424f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/option-rvc.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=riscv32 -filetype=obj < %s\
+; RUN: | llvm-objdump -triple=riscv32 -mattr=+c -d -riscv-no-aliases -\
+; RUN: | FileCheck -check-prefix=CHECK %s
+
+; This test demonstrates that .option norvc has no effect on codegen when
+; emitting an ELF directly.
+
+define i32 @add(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: add:
+; CHECK: add a0, a1, a0
+; CHECK-NEXT: jalr zero, ra, 0
+ tail call void asm sideeffect ".option rvc", ""()
+ %add = add nsw i32 %b, %a
+ ret i32 %add
+}
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