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| author | Nirav Dave <niravd@google.com> | 2017-11-29 18:06:13 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-11-29 18:06:13 +0000 |
| commit | bafaa53c4daf3c17e89bcbf3ebb9190f52e755c9 (patch) | |
| tree | c18500ad23b4f9d728150a1be4c4b2f7eae710f7 /llvm/test/CodeGen | |
| parent | 5764997ff2ca82be889fab3271c43637f705a272 (diff) | |
| download | bcm5719-llvm-bafaa53c4daf3c17e89bcbf3ebb9190f52e755c9.tar.gz bcm5719-llvm-bafaa53c4daf3c17e89bcbf3ebb9190f52e755c9.zip | |
[ARM][DAG] Revert Disable post-legalization store merge for ARM
Partially reverting enabling of post-legalization store merge
(r319036) for just ARM backend as it is causing incorrect code
in some Thumb2 cases.
llvm-svn: 319331
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-promote.ll | 50 |
1 files changed, 19 insertions, 31 deletions
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll index da2a1df9522..257d99d1192 100644 --- a/llvm/test/CodeGen/ARM/fp16-promote.ll +++ b/llvm/test/CodeGen/ARM/fp16-promote.ll @@ -817,37 +817,25 @@ define void @test_fmuladd(half* %p, half* %q, half* %r) #0 { ; CHECK-ALL-LABEL: test_insertelement: ; CHECK-ALL: sub sp, sp, #8 - -; CHECK-VFP: and -; CHECK-VFP: mov -; CHECK-VFP: ldrd -; CHECK-VFP: orr -; CHECK-VFP: ldrh -; CHECK-VFP: stm -; CHECK-VFP: strh -; CHECK-VFP: ldm -; CHECK-VFP: stm - -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP: ldrh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: mov -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: orr -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: ldrh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh -; CHECK-NOVFP-DAG: strh - +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL: ldrh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: mov +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: orr +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: ldrh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh +; CHECK-ALL-DAG: strh ; CHECK-ALL: add sp, sp, #8 define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 { %a = load half, half* %p, align 2 |
