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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2016-11-22 01:42:34 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2016-11-22 01:42:34 +0000 |
| commit | ae0f6620e4fd73f6ba4557814e28c526cf2fa6e6 (patch) | |
| tree | 840427d7c0d554b01441821932cb2a3e09dd6f4e /llvm/test/CodeGen | |
| parent | bb536fee3218c8c4efe40cce4755ebc7ac126e66 (diff) | |
| download | bcm5719-llvm-ae0f6620e4fd73f6ba4557814e28c526cf2fa6e6.tar.gz bcm5719-llvm-ae0f6620e4fd73f6ba4557814e28c526cf2fa6e6.zip | |
[AMDGPU] Fix multiple vreg definitions in si-lower-control-flow
Differential Revision: https://reviews.llvm.org/D26939
llvm-svn: 287608
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/valu-i1.ll | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll index 40a66c26675..86d96435a29 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll @@ -14,7 +14,7 @@ ; GCN-DAG: v_cmp_lt_f32_e32 vcc, ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]] ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]] -; GCN: s_xor_b64 [[SAVED]], exec, [[SAVED]] +; GCN: s_xor_b64 {{s\[[0-9]+:[0-9]+\]}}, exec, [[SAVED]] ; ; TODO: The following sequence is a bug (missing s_endpgm)! ; diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll index f2324b82422..0cc9f064ed3 100644 --- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll @@ -9,8 +9,8 @@ declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; waitcnt should be inserted after exec modification ; SI: v_cmp_lt_i32_e32 vcc, 0, -; SI-NEXT: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc -; SI-NEXT: s_xor_b64 [[SAVE]], exec, [[SAVE]] +; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc +; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]] ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[FLOW_BB]] @@ -24,9 +24,9 @@ declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; v_mov should be after exec modification ; SI: [[FLOW_BB]]: -; SI-NEXT: s_or_saveexec_b64 [[SAVE]], [[SAVE]] +; SI-NEXT: s_or_saveexec_b64 [[SAVE3:s\[[0-9]+:[0-9]+\]]], [[SAVE2]] ; SI-NEXT: v_mov_b32_e32 v{{[0-9]+}} -; SI-NEXT: s_xor_b64 exec, exec, [[SAVE]] +; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]] ; SI-NEXT: ; mask branch ; define void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 { @@ -152,7 +152,7 @@ exit: ; SI-DAG: v_cmp_ne_u32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]] ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]] ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]] -; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]] +; SI: s_xor_b64 [[ORNEG3:s\[[0-9]+:[0-9]+\]]], exec, [[ORNEG2]] ; SI: s_cbranch_execz [[LABEL_FLOW:BB[0-9]+_[0-9]+]] ; SI: BB{{[0-9]+_[0-9]+}}: ; %bb20 @@ -162,8 +162,8 @@ exit: ; SI: [[LABEL_FLOW]]: ; SI-NEXT: ; in Loop: Header=[[LABEL_LOOP]] -; SI-NEXT: s_or_b64 exec, exec, [[ORNEG2]] -; SI-NEXT: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]] +; SI-NEXT: s_or_b64 exec, exec, [[ORNEG3]] +; SI-NEXT: s_or_b64 [[COND_STATE]], [[ORNEG3]], [[TMP]] ; SI-NEXT: s_andn2_b64 exec, exec, [[COND_STATE]] ; SI-NEXT: s_cbranch_execnz [[LABEL_LOOP]] |
