diff options
| author | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 14:42:37 +0000 |
|---|---|---|
| committer | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 14:42:37 +0000 |
| commit | adda5b2d2b4785a1d76334532845ad14c339921f (patch) | |
| tree | 9369ffeb94484f94c9ec6de5d69196870e846e64 /llvm/test/CodeGen | |
| parent | c0681d2b0e76fe49f541f31b95cc235c984c68ff (diff) | |
| download | bcm5719-llvm-adda5b2d2b4785a1d76334532845ad14c339921f.tar.gz bcm5719-llvm-adda5b2d2b4785a1d76334532845ad14c339921f.zip | |
[PPC] add intrinsics for vec extract exp/significand and vec test data class.
Differential Revision: https://reviews.llvm.org/D26272
llvm-svn: 286829
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-p9.ll | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsx-p9.ll b/llvm/test/CodeGen/PowerPC/vsx-p9.ll index 9d546ec6b15..307859c7030 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-p9.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-p9.ll @@ -260,4 +260,75 @@ declare <4 x i32> @llvm.ppc.altivec.vrlwnm(<4 x i32>, <4 x i32>) ; Function Attrs: nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vrldnm(<2 x i64>, <2 x i64>) +define <4 x i32> @testXVXEXPSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXEXPSP +; CHECK: xvxexpsp 34, 34 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXEXPDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXEXPDP +; CHECK xvxexpdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVXSIGSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testXVXSIGSP +; CHECK xvxsigsp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVXSIGDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testXVXSIGDP +; CHECK xvxsigdp 34, 34 +; CHECK blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testXVTSTDCSP(<4 x float> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127) + ret <4 x i32> %0 +; CHECK-LABEL: testXVTSTDCSP +; CHECK: xvtstdcsp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b) + +; Function Attrs: nounwind readnone +define <2 x i64> @testXVTSTDCDP(<2 x double> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127) + ret <2 x i64> %0 +; CHECK-LABEL: testXVTSTDCDP +; CHECK: xvtstdcdp 34, 34, 127 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b) + declare void @sink(...) |
