[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics

AMDGPU backend errors with "unsupported call to function" upon
encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch
adds custom lowering to avoid that error on both R600 and SI.

Reviewers: arsenm, jvesely

Subscribers: tstellar

Differential Revision: https://reviews.llvm.org/D29942

llvm-svn: 319025

4 files changed, 320 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
new file mode 100644
index 00000000000..d64c0bba412
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
@@ -0,0 +1,71 @@
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
+
+declare half @llvm.log.f16(half %a)
+declare <2 x half> @llvm.log.v2f16(<2 x half> %a)
+
+; FUNC-LABEL: {{^}}log_f16
+; SI:     buffer_load_ushort v[[A_F16_0:[0-9]+]]
+; VI:     flat_load_ushort v[[A_F16_0:[0-9]+]]
+; GFX9:   global_load_ushort v[[A_F16_0:[0-9]+]]
+; SI:     v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:     v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:     v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3f317218, v[[R_F32_0]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
+; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
+; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]]
+; SI:     buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
+; VI:     flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
+; GFX9:   global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
+define void @log_f16(
+    half addrspace(1)* %r,
+    half addrspace(1)* %a) {
+entry:
+  %a.val = load half, half addrspace(1)* %a
+  %r.val = call half @llvm.log.f16(half %a.val)
+  store half %r.val, half addrspace(1)* %r
+  ret void
+}
+
+; FUNC-LABEL: {{^}}log_v2f16
+; SI:     buffer_load_dword v[[A_F16_0:[0-9]+]]
+; VI:     flat_load_dword v[[A_F16_0:[0-9]+]]
+; GFX9:   global_load_dword v[[A_F16_0:[0-9]+]]
+; SI:     v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3f317218
+; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x398c
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
+; SI:     v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:     v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
+; SI:     v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:     v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
+; SI:     v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
+; GFX9:   v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
+; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; VI:     v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
+; VI:     v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9:   v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
+; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
+; SI:     v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
+; SI-NOT: v_and_b32_e32
+; SI:     v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
+; VI-NOT: v_and_b32_e32
+; VI:     v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
+; GFX9:   v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
+; GFX9:   v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
+; SI:     buffer_store_dword v[[R_F32_5]]
+; VI:     flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
+; GFX9:   global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
+define void @log_v2f16(
+    <2 x half> addrspace(1)* %r,
+    <2 x half> addrspace(1)* %a) {
+entry:
+  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
+  %r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val)
+  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
+  ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
new file mode 100644
index 00000000000..8018bf277cf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -0,0 +1,89 @@
+; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC  %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 --check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}test:
+; EG: LOG_IEEE
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f317218, v{{[0-9]+}}
+define void @test(float addrspace(1)* %out, float %in) {
+entry:
+   %res = call float @llvm.log.f32(float %in)
+   store float %res, float addrspace(1)* %out
+   ret void
+}
+
+; FUNC-LABEL: {{^}}testv2:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %res = call <2 x float> @llvm.log.v2f32(<2 x float> %in)
+  store <2 x float> %res, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}testv4:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3f317218
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
+entry:
+  %res = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
+  store <4 x float> %res, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+declare float @llvm.log.f32(float) readnone
+declare <2 x float> @llvm.log.v2f32(<2 x float>) readnone
+declare <4 x float> @llvm.log.v4f32(<4 x float>) readnone
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
new file mode 100644
index 00000000000..70cac1d2539
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
@@ -0,0 +1,71 @@
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
+
+declare half @llvm.log10.f16(half %a)
+declare <2 x half> @llvm.log10.v2f16(<2 x half> %a)
+
+; GCN-LABEL: {{^}}log10_f16
+; SI:     buffer_load_ushort v[[A_F16_0:[0-9]+]]
+; VI:     flat_load_ushort v[[A_F16_0:[0-9]+]]
+; GFX9:   global_load_ushort v[[A_F16_0:[0-9]+]]
+; SI:     v_mov_b32_e32 v[[A_F32_1:[0-9]+]]
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:     v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:     v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3e9a209a, v[[R_F32_0]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
+; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
+; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x34d1, v[[R_F16_0]]
+; SI:     buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
+; VI:     flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
+; GFX9:   global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
+define void @log10_f16(
+    half addrspace(1)* %r,
+    half addrspace(1)* %a) {
+entry:
+  %a.val = load half, half addrspace(1)* %a
+  %r.val = call half @llvm.log10.f16(half %a.val)
+  store half %r.val, half addrspace(1)* %r
+  ret void
+}
+
+; GCN-LABEL: {{^}}log10_v2f16
+; SI:     buffer_load_dword v[[A_F16_0:[0-9]+]]
+; VI:     flat_load_dword v[[A_F16_0:[0-9]+]]
+; GFX9:   global_load_dword v[[A_F16_0:[0-9]+]]
+; SI:     v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x3e9a209a
+; VIGFX9: v_mov_b32_e32 v[[A_F32_2:[0-9]+]], 0x34d1
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
+; SI:     v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
+; SI:     v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
+; SI:     v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
+; SI:     v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
+; SI:     v_mul_f32_e32 v[[R_F32_6:[0-9]+]], v[[R_F32_1]], v[[A_F32_2]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
+; SI:     v_mul_f32_e32 v[[R_F32_5:[0-9]+]], v[[R_F32_0]], v[[A_F32_2]]
+; SI:     v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
+; GFX9:   v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
+; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; VI:     v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
+; VI:     v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], v[[A_F32_2]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9:   v_mul_f16_e32 v[[R_F32_3:[0-9]+]], v[[R_F16_2]], v[[A_F32_2]]
+; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], v[[R_F16_0]], v[[A_F32_2]]
+; SI:     v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
+; SI-NOT: v_and_b32_e32
+; SI:     v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
+; VI-NOT: v_and_b32_e32
+; VI:     v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
+; GFX9:   v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
+; GFX9:   v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
+; SI:     buffer_store_dword v[[R_F32_5]]
+; VI:     flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
+; GFX9:   global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
+define void @log10_v2f16(
+    <2 x half> addrspace(1)* %r,
+    <2 x half> addrspace(1)* %a) {
+entry:
+  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
+  %r.val = call <2 x half> @llvm.log10.v2f16(<2 x half> %a.val)
+  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
+  ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
new file mode 100644
index 00000000000..1812f47c855
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -0,0 +1,89 @@
+; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC  %s
+; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
+
+; FUNC-LABEL: {{^}}test:
+; EG: LOG_IEEE
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
+define void @test(float addrspace(1)* %out, float %in) {
+entry:
+   %res = call float @llvm.log10.f32(float %in)
+   store float %res, float addrspace(1)* %out
+   ret void
+}
+
+; FUNC-LABEL: {{^}}testv2:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
+entry:
+  %res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
+  store <2 x float> %res, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; FUNC-LABEL: {{^}}testv4:
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; EG: LOG_IEEE
+; FIXME: We should be able to merge these packets together on Cayman so we
+; have a maximum of 4 instructions.
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; SI: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
+; GFX8: v_mov_b32_e32 v[[R_F32_LOG_CONST:[0-9]+]], 0x3e9a209a
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+; GCN: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[R_F32_LOG_CONST]]
+define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
+entry:
+  %res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
+  store <4 x float> %res, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+declare float @llvm.log10.f32(float) readnone
+declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
+declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone