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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-06-20 12:36:34 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-06-20 12:36:34 +0000 |
| commit | a6e2cebf98c5538c4796fedb7354c87cb0dd2c7d (patch) | |
| tree | b32ae0dc42bf213356854274a48c3a5263817ff4 /llvm/test/CodeGen | |
| parent | 916d569b8e20418936ff2056cef63068c681450e (diff) | |
| download | bcm5719-llvm-a6e2cebf98c5538c4796fedb7354c87cb0dd2c7d.tar.gz bcm5719-llvm-a6e2cebf98c5538c4796fedb7354c87cb0dd2c7d.zip | |
[globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
with them. This isn't particularly important yet but it's a small step
towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
an alternate constraint mechanism ConstrainOperandToRegClassAction() which
supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.
Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar
Reviewed By: ab
Subscribers: javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D33590
llvm-svn: 305791
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir index d871a80661a..5e4034d1624 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir @@ -95,7 +95,7 @@ regBankSelected: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } @@ -194,7 +194,7 @@ regBankSelected: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } |
