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authorMichael Kuperstein <michael.m.kuperstein@intel.com>2015-08-19 11:21:43 +0000
committerMichael Kuperstein <michael.m.kuperstein@intel.com>2015-08-19 11:21:43 +0000
commit9fe42604aad42e473d3e9963b929407e8de4da99 (patch)
tree26b078be91c23c65688d3167a170de4e3c3d13d7 /llvm/test/CodeGen
parentdcdab4cd3aca7c587aa2d6cf20ebed1b9abe920e (diff)
downloadbcm5719-llvm-9fe42604aad42e473d3e9963b929407e8de4da99.tar.gz
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[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize
There are some cases where the mul sequence is smaller, but for the most part, using a div is preferable. This does not apply to vectors, since x86 doesn't have vector idiv, and a vector mul/shifts sequence ought to be smaller than a scalarized division. Differential Revision: http://reviews.llvm.org/D12082 llvm-svn: 245431
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/divide-by-constant.ll32
-rw-r--r--llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll13
2 files changed, 45 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/divide-by-constant.ll b/llvm/test/CodeGen/X86/divide-by-constant.ll
index fd07a3f5510..9543d6c4d74 100644
--- a/llvm/test/CodeGen/X86/divide-by-constant.ll
+++ b/llvm/test/CodeGen/X86/divide-by-constant.ll
@@ -94,3 +94,35 @@ define i8 @test9(i8 %x) nounwind {
; CHECK: shrl $11
; CHECK: ret
}
+
+define i32 @testsize1(i32 %x) minsize nounwind {
+entry:
+ %div = sdiv i32 %x, 32
+ ret i32 %div
+; CHECK-LABEL: testsize1:
+; CHECK: divl
+}
+
+define i32 @testsize2(i32 %x) minsize nounwind {
+entry:
+ %div = sdiv i32 %x, 33
+ ret i32 %div
+; CHECK-LABEL: testsize2:
+; CHECK: divl
+}
+
+define i32 @testsize3(i32 %x) minsize nounwind {
+entry:
+ %div = udiv i32 %x, 32
+ ret i32 %div
+; CHECK-LABEL: testsize3:
+; CHECK: shrl
+}
+
+define i32 @testsize4(i32 %x) minsize nounwind {
+entry:
+ %div = udiv i32 %x, 33
+ ret i32 %div
+; CHECK-LABEL: testsize4:
+; CHECK: divl
+}
diff --git a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
index 56855d3c44e..7f71a0c2ea5 100644
--- a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
+++ b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
@@ -13,6 +13,19 @@ entry:
ret <8 x i16> %0
}
+define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {
+entry:
+; CHECK: sdiv_vec8x16_minsize
+; CHECK: psraw $15
+; CHECK: vpsrlw $11
+; CHECK: vpaddw
+; CHECK: vpsraw $5
+; CHECK: ret
+ %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
+ ret <8 x i16> %0
+}
+
+
define <4 x i32> @sdiv_zero(<4 x i32> %var) {
entry:
; CHECK: sdiv_zero
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