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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-20 19:06:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-20 19:06:12 +0000 |
| commit | 9e9101428245c1ce0ee2bdfec58e26011a96950e (patch) | |
| tree | 783c611b29a754f6a6999b22684aacf78c64b73e /llvm/test/CodeGen | |
| parent | d1ceffcd5aa3b7909bb6eda26e7bb99d603facc8 (diff) | |
| download | bcm5719-llvm-9e9101428245c1ce0ee2bdfec58e26011a96950e.tar.gz bcm5719-llvm-9e9101428245c1ce0ee2bdfec58e26011a96950e.zip | |
AMDGPU: Allow 16-bit types in inline asm constraints
llvm-svn: 290193
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inlineasm-16.ll | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inlineasm-16.ll b/llvm/test/CodeGen/AMDGPU/inlineasm-16.ll new file mode 100644 index 00000000000..75f3158937d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/inlineasm-16.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: not llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SICI %s + +; GCN-LABEL: {{^}}s_input_output_i16: +; SICI: error: couldn't allocate output register for constraint 's' +; SICI: error: couldn't allocate input reg for constraint 's' +define void @s_input_output_i16() #0 { + %v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"() + tail call void asm sideeffect "; use $0", "s"(i16 %v) #0 + ret void +} + +; GCN-LABEL: {{^}}v_input_output_i16: +; SICI: error: couldn't allocate output register for constraint 'v' +; SICI: error: couldn't allocate input reg for constraint 'v' +define void @v_input_output_i16() #0 { + %v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0 + tail call void asm sideeffect "; use $0", "v"(i16 %v) + ret void +} + +; GCN-LABEL: {{^}}s_input_output_f16: +; SICI: error: couldn't allocate output register for constraint 's' +; SICI: error: couldn't allocate input reg for constraint 's' +define void @s_input_output_f16() #0 { + %v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0 + tail call void asm sideeffect "; use $0", "s"(half %v) + ret void +} + +; GCN-LABEL: {{^}}v_input_output_f16: +; SICI: error: couldn't allocate output register for constraint 'v' +; SICI: error: couldn't allocate input reg for constraint 'v' +define void @v_input_output_f16() #0 { + %v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0 + tail call void asm sideeffect "; use $0", "v"(half %v) + ret void +} + +attributes #0 = { nounwind } |
