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| author | Mikael Holmen <mikael.holmen@ericsson.com> | 2017-07-06 13:18:21 +0000 |
|---|---|---|
| committer | Mikael Holmen <mikael.holmen@ericsson.com> | 2017-07-06 13:18:21 +0000 |
| commit | 9c3e2eac6a5e48962250342c72989e321e889607 (patch) | |
| tree | b05bcdb1f231d6e1c3aa258d1d78b1d72d92d441 /llvm/test/CodeGen | |
| parent | 13cde86e74941a49ebb43dbb6e6cfe66ecccde28 (diff) | |
| download | bcm5719-llvm-9c3e2eac6a5e48962250342c72989e321e889607.tar.gz bcm5719-llvm-9c3e2eac6a5e48962250342c72989e321e889607.zip | |
[MachineVerifier] Add check that tied physregs aren't different.
Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files.
Original patch by Jesper Antonsson
Reviewers: stoklund, sanjoy, qcolombet
Reviewed By: qcolombet
Subscribers: qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D34394
llvm-svn: 307259
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir new file mode 100644 index 00000000000..1ddf649f76a --- /dev/null +++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir @@ -0,0 +1,22 @@ +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the Machine Verifier detects tied physical registers +# that doesn't match. + +--- | + + define i32 @foo() { + entry: + ret i32 0 + } + +... +--- +name: foo +body: | + bb.0.entry: + liveins: %rdi + + ; CHECK: Tied physical registers must match. + %rbx = AND64rm killed %rdx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags + RETQ %rbx +... |
