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| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-01-23 10:09:39 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-01-23 10:09:39 +0000 |
| commit | 98749e0249892886dcbdf1c972b762660dc09029 (patch) | |
| tree | debaae0bad82fba699608af77ee2153791e45565 /llvm/test/CodeGen | |
| parent | 007b425b776a50b3b8d3caa482bb8ca96c48a80d (diff) | |
| download | bcm5719-llvm-98749e0249892886dcbdf1c972b762660dc09029.tar.gz bcm5719-llvm-98749e0249892886dcbdf1c972b762660dc09029.zip | |
[mips] Properly select abs and sqrt instructions
- Alter abs for micromips to have both AFGR64 and FGR64
variants, same as sqrt
- Remove sqrt and abs from MicroMips32r6InstrInfo.td,
use micromips FGR64 variants
- Restrict non-micromips abs/sqrt with NotInMicroMips
predicate
Differential revision: https://reviews.llvm.org/D41439
llvm-svn: 323184
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/abs.ll | 28 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll | 29 |
2 files changed, 57 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/abs.ll b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll new file mode 100644 index 00000000000..3ae8525ec18 --- /dev/null +++ b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 + +define float @abs_s(float %a) { +; MIPS32: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S +; MIPS32FP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S +; MM: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM +; MMFP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM +; MMR6: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM + %ret = call float @llvm.fabs.f32(float %a) + ret float %ret +} + +define double @abs_d(double %a) { +; MIPS32: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32 +; MIPS32FP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64 +; MM: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32_MM +; MMFP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM +; MMR6: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM + %ret = call double @llvm.fabs.f64(double %a) + ret double %ret +} + +declare float @llvm.fabs.f32(float %a) +declare double @llvm.fabs.f64(double %a) diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll index 1a8892de0ee..05776886dd9 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll @@ -1,6 +1,11 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 define float @sqrt_fn(float %value) #0 { entry: @@ -11,3 +16,27 @@ entry: declare float @sqrtf(float) ; CHECK: sqrt.s $f0, $f12 + + +define float @sqrt_s(float %a) { +; MIPS32: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S +; MIPS32FP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S +; MM: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM +; MMFP64: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM +; MMR6: sqrt.s {{.*}} # <MCInst #{{[0-9]+}} FSQRT_S_MM + %ret = call float @llvm.sqrt.f32(float %a) + ret float %ret +} + +define double @sqrt_d(double %a) { +; MIPS32: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32 +; MIPS32FP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64 +; MM: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D32_MM +; MMFP64: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM +; MMR6: sqrt.d {{.*}} # <MCInst #{{[0-9]+}} FSQRT_D64_MM + %ret = call double @llvm.sqrt.f64(double %a) + ret double %ret +} + +declare float @llvm.sqrt.f32(float %a) +declare double @llvm.sqrt.f64(double %a) |
