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| author | Sam Parker <sam.parker@arm.com> | 2018-09-13 14:48:10 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2018-09-13 14:48:10 +0000 |
| commit | 96f77f142ba9b399435b09ac4a77af00f641d4e9 (patch) | |
| tree | 5cae14542363d5405bb744b6a1d816c9e9889143 /llvm/test/CodeGen | |
| parent | c96cb25a8ba7baac5ad03545c5823032dbfa9ba4 (diff) | |
| download | bcm5719-llvm-96f77f142ba9b399435b09ac4a77af00f641d4e9.tar.gz bcm5719-llvm-96f77f142ba9b399435b09ac4a77af00f641d4e9.zip | |
[ARM] Fix FixConst for ARMCodeGenPrepare
Part of FixConsts wrongly assumes either a 8- or 16-bit constant
which can result in the wrong constants being generated during
promotion.
Differential Revision: https://reviews.llvm.org/D52032
llvm-svn: 342140
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/arm-cgp-icmps.ll | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/arm-cgp-icmps.ll b/llvm/test/CodeGen/ARM/arm-cgp-icmps.ll index a24cdab559f..7ecd3ac6fc4 100644 --- a/llvm/test/CodeGen/ARM/arm-cgp-icmps.ll +++ b/llvm/test/CodeGen/ARM/arm-cgp-icmps.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP +; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP ; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP ; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM @@ -279,3 +279,12 @@ entry: ret i32 %res } +; CHECK-COMMON-LABEL: icmp_i15 +; CHECK-COMMON: movw [[MINUS_ONE:r[0-9]+]], #32767 +define i32 @icmp_i15(i15 zeroext %arg0, i15 zeroext %arg1) { + %xor = xor i15 %arg0, -1 + %cmp = icmp eq i15 %xor, %arg1 + %res = select i1 %cmp, i32 21, i32 42 + ret i32 %res +} + |
