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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-30 18:58:47 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-30 18:58:47 +0000 |
| commit | 9161d474763335fab36f31c21824df2a811ed098 (patch) | |
| tree | c0e0684b213c5a7b591111c8c81cd6433ddf168b /llvm/test/CodeGen | |
| parent | c787e4eb1ec1ea8b9c8ce8facdb7c497a9e277e9 (diff) | |
| download | bcm5719-llvm-9161d474763335fab36f31c21824df2a811ed098.tar.gz bcm5719-llvm-9161d474763335fab36f31c21824df2a811ed098.zip | |
[Hexagon] Adding reg-reg indexed load forms.
llvm-svn: 224997
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/block-addr.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/Hexagon/block-addr.ll b/llvm/test/CodeGen/Hexagon/block-addr.ll index 54a12bf4844..dc0d6e60fd2 100644 --- a/llvm/test/CodeGen/Hexagon/block-addr.ll +++ b/llvm/test/CodeGen/Hexagon/block-addr.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}}) -; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+<<#[0-9]+}}) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}} + r{{[0-9]+<<#[0-9]+}}) ; CHECK: jumpr r{{[0-9]+}} define void @main() #0 { diff --git a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index ca6df88a552..729d79f55a6 100644 --- a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -4,7 +4,7 @@ ; load word define i32 @load_w(i32* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i32* %a, i32 %tmp @@ -15,7 +15,7 @@ entry: ; load unsigned half word define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i16* %a, i32 %tmp @@ -26,7 +26,7 @@ entry: ; load signed half word define i32 @load_h(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i16* %a, i32 %tmp @@ -38,7 +38,7 @@ entry: ; load unsigned byte define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i8* %a, i32 %tmp @@ -49,7 +49,7 @@ entry: ; load signed byte define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i8* %a, i32 %tmp @@ -61,7 +61,7 @@ entry: ; load doubleword define i64 @load_d(i64* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i64* %a, i32 %tmp |
