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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-01-21 17:07:06 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-01-21 17:07:06 +0000 |
| commit | 8f09e9f7c5b356747df93a45a3dc30b18607e86d (patch) | |
| tree | 17e6cb8e73f7d68afa5ccff33f413f9d602a7f7a /llvm/test/CodeGen | |
| parent | 469e2ee83af2a06ed84341d21521e07bd0a3ce8e (diff) | |
| download | bcm5719-llvm-8f09e9f7c5b356747df93a45a3dc30b18607e86d.tar.gz bcm5719-llvm-8f09e9f7c5b356747df93a45a3dc30b18607e86d.zip | |
[X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.
Now that we can fully specify extload legality, we can declare them
legal for the PMOVSX/PMOVZX instructions. This for instance enables
a DAGCombine to fire on code such as
(and (<zextload-equivalent> ...), <redundant mask>)
to turn it into:
(zextload ...)
as seen in the testcase changes.
There is one regression, in widen_load-2.ll: we're no longer able
to do store-to-load forwarding with illegal extload memory types.
This will be addressed separately.
Differential Revision: http://reviews.llvm.org/D6533
llvm-svn: 226676
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pointer-vector.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/widen_load-2.ll | 5 |
3 files changed, 4 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll b/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll index 44eb42adb9f..4054931be37 100644 --- a/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll +++ b/llvm/test/CodeGen/X86/avx2-pmovx-256-old-shuffle.ll @@ -15,8 +15,6 @@ define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) { ; CHECK-LABEL: test_avx2_pmovx_256 ; We really don't care about the generated code. ; CHECK: vpmovzxbd -; CHECK: vpbroadcastd -; CHECK: vpand ; CHECK: vcvtdq2ps ; CHECK: vmovups ; CHECK: vzeroupper diff --git a/llvm/test/CodeGen/X86/pointer-vector.ll b/llvm/test/CodeGen/X86/pointer-vector.ll index 0ee99875264..5e0c2dae083 100644 --- a/llvm/test/CodeGen/X86/pointer-vector.ll +++ b/llvm/test/CodeGen/X86/pointer-vector.ll @@ -81,8 +81,7 @@ define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind { entry: %G = load <4 x i8>* %p ;CHECK: movl -;CHECK: pmovzxbd -;CHECK: pand +;CHECK: pmovzxbd (% %K = inttoptr <4 x i8> %G to <4 x i32*> ;CHECK: ret ret <4 x i32*> %K diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll index a3cc4079117..c6bd96421d7 100644 --- a/llvm/test/CodeGen/X86/widen_load-2.ll +++ b/llvm/test/CodeGen/X86/widen_load-2.ll @@ -191,8 +191,9 @@ define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pa ; CHECK-NEXT: movd %[[CONSTANT1]], %e[[R1:[abcd]]]x ; CHECK-NEXT: movw %[[R1]]x, (%[[PTR1:.*]]) ; CHECK-NEXT: movb $1, 2(%[[PTR1]]) -; CHECK-NEXT: pmovzxbd (%[[PTR0]]), %[[X0:xmm[0-9]+]] -; CHECK-NEXT: pand {{.*}}, %[[X0]] +; CHECK-NEXT: movl (%[[PTR0]]), [[TMP1:%e[abcd]+x]] +; CHECK-NEXT: movl [[TMP1]], [[TMP2:.*]] +; CHECK-NEXT: pmovzxbd [[TMP2]], %[[X0:xmm[0-9]+]] ; CHECK-NEXT: pextrd $1, %[[X0]], %e[[R0:[abcd]]]x ; CHECK-NEXT: shrl %e[[R0]]x ; CHECK-NEXT: movd %[[X0]], %e[[R1:[abcd]]]x |
