[ARM] Add scheduling classes for VFNM[AS]

The VFNM[AS] instructions did not have scheduling information attached, which
was causing assertion failures with the Cortex-A57 scheduling model and
-fp-contract=fast, because the Cortex-A57 sched model claims to be complete.

Differential Revision: https://reviews.llvm.org/D34139

llvm-svn: 305288

1 files changed, 38 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll
index 5f914323861..e234e179ed0 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll
@@ -156,3 +156,41 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2
   %sub2 = fsub <2 x float> %sub1, %mul3
   ret <2 x float> %sub2
 }
+
+define float @Test5(float %f1, float %f2, float %f3) {
+; CHECK:       ********** MI Scheduling **********
+; CHECK:       Test5:BB#0
+
+; CHECK-DEFAULT: VNMLS
+; CHECK-FAST:    VFNMS
+; CHECK:       Latency            : 9
+; CHECK:       Successors:
+; CHECK:       data
+; > VMLAS not-optimized latency to VMOVRS = 9
+; CHECK-SAME:  Latency=9
+
+; f1 * f2 - f3  ==>  VNMLS/VFNMS
+  %mul = fmul float %f1, %f2
+  %sub = fsub float %mul, %f3
+  ret float %sub
+}
+
+
+define float @Test6(float %f1, float %f2, float %f3) {
+; CHECK:       ********** MI Scheduling **********
+; CHECK:       Test6:BB#0
+
+; CHECK-DEFAULT: VNMLA
+; CHECK-FAST:    VFNMA
+; CHECK:       Latency            : 9
+; CHECK:       Successors:
+; CHECK:       data
+; > VMLAS not-optimized latency to VMOVRS = 9
+; CHECK-SAME:  Latency=9
+
+; f1 * f2 - f3  ==>  VNMLA/VFNMA
+  %mul = fmul float %f1, %f2
+  %sub1 = fsub float -0.0, %mul
+  %sub2 = fsub float %sub1, %f2
+  ret float %sub2
+}