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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-04-11 13:37:25 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-04-11 13:37:25 +0000 |
| commit | 7bcb5720fd38b882f514b428d36fdbbef417ab45 (patch) | |
| tree | 366b8f252fa22126e67347eeb275b6c01c59ce42 /llvm/test/CodeGen | |
| parent | d74ebe22db891a964d77082e42ad18f28d93610a (diff) | |
| download | bcm5719-llvm-7bcb5720fd38b882f514b428d36fdbbef417ab45.tar.gz bcm5719-llvm-7bcb5720fd38b882f514b428d36fdbbef417ab45.zip | |
[AArch64] Add test case for r329797
Forgot to add a test case in the previous commit.
llvm-svn: 329805
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir b/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir index 686fbe88911..5cf3bf99b1f 100644 --- a/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir +++ b/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir @@ -19,3 +19,20 @@ body: | bb.1: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp, $lr RET_ReallyLR implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27, implicit $x28 +... +--- +name: fpDoesNotFit +# CHECK-LABEL: name: fpDoesNotFit +tracksRegLiveness: true +frameInfo: + hasStackMap: true +# set to true to force hasFP to true. +stack: + - { id: 0, name: '', size: 4096, alignment: 8 } + - { id: 1, name: '', size: 32761, alignment: 8 } +body: | + bb.0: + STRXui undef $x8, %stack.0, -34 + ; Pick SP here. Picking FP will require scavenging a register. + ; CHECK: STRXui undef $x8, $sp, 4062 + RET_ReallyLR |
