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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-22 22:23:32 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-22 22:23:32 +0000 |
| commit | 7b6c5d28f54cc5b833576e52d0f80f2ee6ea582d (patch) | |
| tree | e2bb5065599f5151eb70cc7147f40444123643ad /llvm/test/CodeGen | |
| parent | 639d7b68d656d73bf8ee0b05bc9476502dcdb21d (diff) | |
| download | bcm5719-llvm-7b6c5d28f54cc5b833576e52d0f80f2ee6ea582d.tar.gz bcm5719-llvm-7b6c5d28f54cc5b833576e52d0f80f2ee6ea582d.zip | |
AMDGPU: Don't add emergency stack slot if all spills are SGPR->VGPR
This should avoid reporting any stack needs to be allocated in the
case where no stack is truly used. An unused stack slot is still
left around in other cases where there are real stack objects
but no spilling occurs.
llvm-svn: 295891
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll index bccddcd9687..bcaaba72403 100644 --- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll @@ -18,13 +18,12 @@ ; GCN: s_mov_b32 m0 ; Make sure scratch space isn't being used for SGPR->VGPR spills -; FIXME: Seem to be leaving behind unused emergency slot. ; Writing to M0 from an SMRD instruction will hang the GPU. ; GCN-NOT: s_buffer_load_dword m0 ; GCN: s_endpgm -; TOVGPR: ScratchSize: 4{{$}} +; TOVGPR: ScratchSize: 0{{$}} define amdgpu_ps void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { main_body: %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 @@ -768,7 +767,7 @@ ENDIF66: ; preds = %LOOP65 ; GCN-LABEL: {{^}}main1: ; GCN: s_endpgm -; TOVGPR: ScratchSize: 4{{$}} +; TOVGPR: ScratchSize: 0{{$}} define amdgpu_ps void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { main_body: %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 |
