ARM: update even more tests

More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

llvm-svn: 205545

7 files changed, 20 insertions, 8 deletions

diff --git a/llvm/test/CodeGen/ARM/argaddr.ll b/llvm/test/CodeGen/ARM/argaddr.ll
index 116a32f9c74..40bc5e0b82a 100644
--- a/llvm/test/CodeGen/ARM/argaddr.ll
+++ b/llvm/test/CodeGen/ARM/argaddr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm
+; RUN: llc -mtriple=arm-eabi %s -o /dev/null
 
 define void @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
 entry:
diff --git a/llvm/test/CodeGen/ARM/movt.ll b/llvm/test/CodeGen/ARM/movt.ll
index 735d949f755..94c022ee271 100644
--- a/llvm/test/CodeGen/ARM/movt.ll
+++ b/llvm/test/CodeGen/ARM/movt.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 ; rdar://7317664
 
 define i32 @t(i32 %X) nounwind {
diff --git a/llvm/test/CodeGen/ARM/mul.ll b/llvm/test/CodeGen/ARM/mul.ll
index 466a8020acc..5e150b00172 100644
--- a/llvm/test/CodeGen/ARM/mul.ll
+++ b/llvm/test/CodeGen/ARM/mul.ll
@@ -1,11 +1,12 @@
-; RUN: llc < %s -march=arm | grep mul | count 2
-; RUN: llc < %s -march=arm | grep lsl | count 2
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 
 define i32 @f1(i32 %u) {
     %tmp = mul i32 %u, %u
     ret i32 %tmp
 }
 
+; CHECK: mul
+
 define i32 @f2(i32 %u, i32 %v) {
     %tmp = mul i32 %u, %v
     ret i32 %tmp
@@ -16,7 +17,16 @@ define i32 @f3(i32 %u) {
         ret i32 %tmp
 }
 
+; CHECK: mul
+; CHECK: lsl
+
 define i32 @f4(i32 %u) {
 	%tmp = mul i32 %u, 4
         ret i32 %tmp
 }
+
+; CHECK-NOT: mul
+
+; CHECK: lsl
+; CHECK-NOT: lsl
+
diff --git a/llvm/test/CodeGen/ARM/ret_i64_arg2.ll b/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
index c51d2b88a25..531360008ba 100644
--- a/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
+++ b/llvm/test/CodeGen/ARM/ret_i64_arg2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
+; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
 
 define i64 @test_i64(i64 %a1, i64 %a2) {
         ret i64 %a2
diff --git a/llvm/test/CodeGen/ARM/ret_i64_arg3.ll b/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
index 602997ea360..ce8da0ab818 100644
--- a/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
+++ b/llvm/test/CodeGen/ARM/ret_i64_arg3.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
+; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
 
 define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) {
         ret i64 %a3
diff --git a/llvm/test/CodeGen/ARM/smml.ll b/llvm/test/CodeGen/ARM/smml.ll
index 99df0d4c96b..fc73eb76d77 100644
--- a/llvm/test/CodeGen/ARM/smml.ll
+++ b/llvm/test/CodeGen/ARM/smml.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
+
 define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
 entry:
 ; CHECK-NOT: smmls
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-select.ll b/llvm/test/CodeGen/Thumb2/thumb2-select.ll
index 949b6116ca3..105c2672ee1 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-select.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-select.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 -show-mc-encoding | FileCheck %s
+; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 -show-mc-encoding %s -o - \
+; RUN:  | FileCheck %s
 
 define i32 @f1(i32 %a.s) {
 entry: