[Hexagon] Handle lowering of SETCC via setCondCodeAction

It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.

llvm-svn: 324348

2 files changed, 30 insertions, 60 deletions

diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
index b4d78d5e50f..dd15518dbd8 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
@@ -13,8 +13,7 @@ define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_01:
 ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
-; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]])
-; CHECK: v0 = vmux(q[[Q011]],v0,v1)
+; CHECK: v0 = vmux(q[[Q010]],v1,v0)
 define <128 x i8> @test_01(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ne <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -32,8 +31,7 @@ define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_03:
 ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
-; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q030]],v1,v0)
 define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sle <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -51,8 +49,7 @@ define <128 x i8> @test_04(<128 x i8> %v0, <128 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_05:
 ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
-; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]])
-; CHECK: v0 = vmux(q[[Q051]],v0,v1)
+; CHECK: v0 = vmux(q[[Q050]],v1,v0)
 define <128 x i8> @test_05(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -70,8 +67,7 @@ define <128 x i8> @test_06(<128 x i8> %v0, <128 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_07:
 ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
-; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]])
-; CHECK: v0 = vmux(q[[Q071]],v0,v1)
+; CHECK: v0 = vmux(q[[Q070]],v1,v0)
 define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp ule <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -89,8 +85,7 @@ define <128 x i8> @test_08(<128 x i8> %v0, <128 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_09:
 ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
-; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]])
-; CHECK: v0 = vmux(q[[Q091]],v0,v1)
+; CHECK: v0 = vmux(q[[Q090]],v1,v0)
 define <128 x i8> @test_09(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp uge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -110,8 +105,7 @@ define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_11:
 ; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h)
-; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]])
-; CHECK: v0 = vmux(q[[Q111]],v0,v1)
+; CHECK: v0 = vmux(q[[Q110]],v1,v0)
 define <64 x i16> @test_11(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ne <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
@@ -129,8 +123,7 @@ define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_13:
 ; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h)
-; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q130]],v1,v0)
 define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sle <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
@@ -148,8 +141,7 @@ define <64 x i16> @test_14(<64 x i16> %v0, <64 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_15:
 ; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h)
-; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]])
-; CHECK: v0 = vmux(q[[Q151]],v0,v1)
+; CHECK: v0 = vmux(q[[Q150]],v1,v0)
 define <64 x i16> @test_15(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp sge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
@@ -167,8 +159,7 @@ define <64 x i16> @test_16(<64 x i16> %v0, <64 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_17:
 ; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh)
-; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]])
-; CHECK: v0 = vmux(q[[Q171]],v0,v1)
+; CHECK: v0 = vmux(q[[Q170]],v1,v0)
 define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp ule <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
@@ -186,8 +177,7 @@ define <64 x i16> @test_18(<64 x i16> %v0, <64 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_19:
 ; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh)
-; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]])
-; CHECK: v0 = vmux(q[[Q191]],v0,v1)
+; CHECK: v0 = vmux(q[[Q190]],v1,v0)
 define <64 x i16> @test_19(<64 x i16> %v0, <64 x i16> %v1) #0 {
   %t0 = icmp uge <64 x i16> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1
@@ -207,8 +197,7 @@ define <32 x i32> @test_20(<32 x i32> %v0, <32 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_21:
 ; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w)
-; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]])
-; CHECK: v0 = vmux(q[[Q211]],v0,v1)
+; CHECK: v0 = vmux(q[[Q210]],v1,v0)
 define <32 x i32> @test_21(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp ne <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
@@ -226,8 +215,7 @@ define <32 x i32> @test_22(<32 x i32> %v0, <32 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_23:
 ; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w)
-; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q230]],v1,v0)
 define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sle <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
@@ -245,8 +233,7 @@ define <32 x i32> @test_24(<32 x i32> %v0, <32 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_25:
 ; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w)
-; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]])
-; CHECK: v0 = vmux(q[[Q251]],v0,v1)
+; CHECK: v0 = vmux(q[[Q250]],v1,v0)
 define <32 x i32> @test_25(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp sge <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
@@ -264,8 +251,7 @@ define <32 x i32> @test_26(<32 x i32> %v0, <32 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_27:
 ; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw)
-; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]])
-; CHECK: v0 = vmux(q[[Q271]],v0,v1)
+; CHECK: v0 = vmux(q[[Q270]],v1,v0)
 define <32 x i32> @test_27(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp ule <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
@@ -283,8 +269,7 @@ define <32 x i32> @test_28(<32 x i32> %v0, <32 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_29:
 ; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw)
-; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]])
-; CHECK: v0 = vmux(q[[Q291]],v0,v1)
+; CHECK: v0 = vmux(q[[Q290]],v1,v0)
 define <32 x i32> @test_29(<32 x i32> %v0, <32 x i32> %v1) #0 {
   %t0 = icmp uge <32 x i32> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
index 4c0e19791d4..39a117f4ecd 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
@@ -13,8 +13,7 @@ define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_01:
 ; CHECK: q[[Q010:[0-3]]] = vcmp.eq(v0.b,v1.b)
-; CHECK: q[[Q011:[0-9]]] = not(q[[Q010]])
-; CHECK: v0 = vmux(q[[Q011]],v0,v1)
+; CHECK: v0 = vmux(q[[Q010]],v1,v0)
 define <64 x i8> @test_01(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ne <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
@@ -32,8 +31,7 @@ define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_03:
 ; CHECK: q[[Q030:[0-3]]] = vcmp.gt(v0.b,v1.b)
-; CHECK: q[[Q031:[0-9]]] = not(q[[Q030]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q030]],v1,v0)
 define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sle <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
@@ -51,8 +49,7 @@ define <64 x i8> @test_04(<64 x i8> %v0, <64 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_05:
 ; CHECK: q[[Q050:[0-3]]] = vcmp.gt(v1.b,v0.b)
-; CHECK: q[[Q051:[0-9]]] = not(q[[Q050]])
-; CHECK: v0 = vmux(q[[Q051]],v0,v1)
+; CHECK: v0 = vmux(q[[Q050]],v1,v0)
 define <64 x i8> @test_05(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp sge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
@@ -70,8 +67,7 @@ define <64 x i8> @test_06(<64 x i8> %v0, <64 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_07:
 ; CHECK: q[[Q070:[0-3]]] = vcmp.gt(v0.ub,v1.ub)
-; CHECK: q[[Q071:[0-9]]] = not(q[[Q070]])
-; CHECK: v0 = vmux(q[[Q071]],v0,v1)
+; CHECK: v0 = vmux(q[[Q070]],v1,v0)
 define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp ule <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
@@ -89,8 +85,7 @@ define <64 x i8> @test_08(<64 x i8> %v0, <64 x i8> %v1) #0 {
 
 ; CHECK-LABEL: test_09:
 ; CHECK: q[[Q090:[0-3]]] = vcmp.gt(v1.ub,v0.ub)
-; CHECK: q[[Q091:[0-9]]] = not(q[[Q090]])
-; CHECK: v0 = vmux(q[[Q091]],v0,v1)
+; CHECK: v0 = vmux(q[[Q090]],v1,v0)
 define <64 x i8> @test_09(<64 x i8> %v0, <64 x i8> %v1) #0 {
   %t0 = icmp uge <64 x i8> %v0, %v1
   %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1
@@ -110,8 +105,7 @@ define <32 x i16> @test_10(<32 x i16> %v0, <32 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_11:
 ; CHECK: q[[Q110:[0-3]]] = vcmp.eq(v0.h,v1.h)
-; CHECK: q[[Q111:[0-9]]] = not(q[[Q110]])
-; CHECK: v0 = vmux(q[[Q111]],v0,v1)
+; CHECK: v0 = vmux(q[[Q110]],v1,v0)
 define <32 x i16> @test_11(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ne <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
@@ -129,8 +123,7 @@ define <32 x i16> @test_12(<32 x i16> %v0, <32 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_13:
 ; CHECK: q[[Q130:[0-3]]] = vcmp.gt(v0.h,v1.h)
-; CHECK: q[[Q131:[0-9]]] = not(q[[Q130]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q130]],v1,v0)
 define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sle <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
@@ -148,8 +141,7 @@ define <32 x i16> @test_14(<32 x i16> %v0, <32 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_15:
 ; CHECK: q[[Q150:[0-3]]] = vcmp.gt(v1.h,v0.h)
-; CHECK: q[[Q151:[0-9]]] = not(q[[Q150]])
-; CHECK: v0 = vmux(q[[Q151]],v0,v1)
+; CHECK: v0 = vmux(q[[Q150]],v1,v0)
 define <32 x i16> @test_15(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp sge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
@@ -167,8 +159,7 @@ define <32 x i16> @test_16(<32 x i16> %v0, <32 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_17:
 ; CHECK: q[[Q170:[0-3]]] = vcmp.gt(v0.uh,v1.uh)
-; CHECK: q[[Q171:[0-9]]] = not(q[[Q170]])
-; CHECK: v0 = vmux(q[[Q171]],v0,v1)
+; CHECK: v0 = vmux(q[[Q170]],v1,v0)
 define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp ule <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
@@ -186,8 +177,7 @@ define <32 x i16> @test_18(<32 x i16> %v0, <32 x i16> %v1) #0 {
 
 ; CHECK-LABEL: test_19:
 ; CHECK: q[[Q190:[0-3]]] = vcmp.gt(v1.uh,v0.uh)
-; CHECK: q[[Q191:[0-9]]] = not(q[[Q190]])
-; CHECK: v0 = vmux(q[[Q191]],v0,v1)
+; CHECK: v0 = vmux(q[[Q190]],v1,v0)
 define <32 x i16> @test_19(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %t0 = icmp uge <32 x i16> %v0, %v1
   %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1
@@ -207,8 +197,7 @@ define <16 x i32> @test_20(<16 x i32> %v0, <16 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_21:
 ; CHECK: q[[Q210:[0-3]]] = vcmp.eq(v0.w,v1.w)
-; CHECK: q[[Q211:[0-9]]] = not(q[[Q210]])
-; CHECK: v0 = vmux(q[[Q211]],v0,v1)
+; CHECK: v0 = vmux(q[[Q210]],v1,v0)
 define <16 x i32> @test_21(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp ne <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
@@ -226,8 +215,7 @@ define <16 x i32> @test_22(<16 x i32> %v0, <16 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_23:
 ; CHECK: q[[Q230:[0-3]]] = vcmp.gt(v0.w,v1.w)
-; CHECK: q[[Q231:[0-9]]] = not(q[[Q230]])
-; CHECK: v0 = vmux(q[[Q031]],v0,v1)
+; CHECK: v0 = vmux(q[[Q230]],v1,v0)
 define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sle <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
@@ -245,8 +233,7 @@ define <16 x i32> @test_24(<16 x i32> %v0, <16 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_25:
 ; CHECK: q[[Q250:[0-3]]] = vcmp.gt(v1.w,v0.w)
-; CHECK: q[[Q251:[0-9]]] = not(q[[Q250]])
-; CHECK: v0 = vmux(q[[Q251]],v0,v1)
+; CHECK: v0 = vmux(q[[Q250]],v1,v0)
 define <16 x i32> @test_25(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp sge <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
@@ -264,8 +251,7 @@ define <16 x i32> @test_26(<16 x i32> %v0, <16 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_27:
 ; CHECK: q[[Q270:[0-3]]] = vcmp.gt(v0.uw,v1.uw)
-; CHECK: q[[Q271:[0-9]]] = not(q[[Q270]])
-; CHECK: v0 = vmux(q[[Q271]],v0,v1)
+; CHECK: v0 = vmux(q[[Q270]],v1,v0)
 define <16 x i32> @test_27(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp ule <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1
@@ -283,8 +269,7 @@ define <16 x i32> @test_28(<16 x i32> %v0, <16 x i32> %v1) #0 {
 
 ; CHECK-LABEL: test_29:
 ; CHECK: q[[Q290:[0-3]]] = vcmp.gt(v1.uw,v0.uw)
-; CHECK: q[[Q291:[0-9]]] = not(q[[Q290]])
-; CHECK: v0 = vmux(q[[Q291]],v0,v1)
+; CHECK: v0 = vmux(q[[Q290]],v1,v0)
 define <16 x i32> @test_29(<16 x i32> %v0, <16 x i32> %v1) #0 {
   %t0 = icmp uge <16 x i32> %v0, %v1
   %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1