diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-07-23 03:59:37 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-07-23 03:59:37 +0000 |
| commit | 6912d7faa38ca4592327295088b439c5bdb6a0db (patch) | |
| tree | 4d41bae3e281052d3d9b9591ad1105c83e9efd2e /llvm/test/CodeGen | |
| parent | 4e6dcf73f9189ab54f1d42abf1d83f3744b10e3c (diff) | |
| download | bcm5719-llvm-6912d7faa38ca4592327295088b439c5bdb6a0db.tar.gz bcm5719-llvm-6912d7faa38ca4592327295088b439c5bdb6a0db.zip | |
[X86] Add patterns for memory forms of SARX/SHLX/SHRX with careful complexity adjustment to keep shift by immediate using the legacy instructions.
These patterns were only missing to favor using the legacy instructions when the shift was a constant. With careful adjustment of the pattern complexity we can make sure the immediate instructions still have priority over these patterns.
llvm-svn: 308834
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/shift-bmi2.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/X86/shift-bmi2.ll b/llvm/test/CodeGen/X86/shift-bmi2.ll index f9bca503218..008dce7bb60 100644 --- a/llvm/test/CodeGen/X86/shift-bmi2.ll +++ b/llvm/test/CodeGen/X86/shift-bmi2.ll @@ -36,9 +36,9 @@ define i32 @shl32i(i32 %x) nounwind uwtable readnone { define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone { ; BMI2-LABEL: shl32p: ; BMI2: # BB#0: -; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al -; BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx -; BMI2-NEXT: shlxl %eax, (%ecx), %eax +; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl +; BMI2-NEXT: shlxl %ecx, (%eax), %eax ; BMI2-NEXT: retl ; ; BMI264-LABEL: shl32p: @@ -126,9 +126,9 @@ define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone { define i32 @lshr32p(i32* %p, i32 %shamt) nounwind uwtable readnone { ; BMI2-LABEL: lshr32p: ; BMI2: # BB#0: -; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al -; BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx -; BMI2-NEXT: shrxl %eax, (%ecx), %eax +; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl +; BMI2-NEXT: shrxl %ecx, (%eax), %eax ; BMI2-NEXT: retl ; ; BMI264-LABEL: lshr32p: @@ -177,9 +177,9 @@ define i32 @ashr32(i32 %x, i32 %shamt) nounwind uwtable readnone { define i32 @ashr32p(i32* %p, i32 %shamt) nounwind uwtable readnone { ; BMI2-LABEL: ashr32p: ; BMI2: # BB#0: -; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al -; BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx -; BMI2-NEXT: sarxl %eax, (%ecx), %eax +; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl +; BMI2-NEXT: sarxl %ecx, (%eax), %eax ; BMI2-NEXT: retl ; ; BMI264-LABEL: ashr32p: |
