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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-09 16:36:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-09 16:36:31 +0000 |
| commit | 689f325099bf84da75275aecc1bd01580b78f925 (patch) | |
| tree | 20ae8880685982a58208e5767ce4bee0bd4519a4 /llvm/test/CodeGen | |
| parent | 13ccc8f1bc2fbf4da6f22973916f7cca91e44656 (diff) | |
| download | bcm5719-llvm-689f325099bf84da75275aecc1bd01580b78f925.tar.gz bcm5719-llvm-689f325099bf84da75275aecc1bd01580b78f925.zip | |
R600/SI: Keep 64-bit not on SALU
llvm-svn: 210476
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/R600/sub.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/xor.ll | 40 |
2 files changed, 41 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/R600/sub.ll b/llvm/test/CodeGen/R600/sub.ll index e321ed67a69..58523d068e5 100644 --- a/llvm/test/CodeGen/R600/sub.ll +++ b/llvm/test/CodeGen/R600/sub.ll @@ -45,7 +45,7 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ;EG-DAG: SUB_INT ;EG-DAG: SUB_INT -;SI: S_XOR_B64 +;SI: S_NOT_B64 ;SI-DAG: S_ADD_I32 ;SI-DAG: S_ADDC_U32 ;SI-DAG: S_ADD_I32 diff --git a/llvm/test/CodeGen/R600/xor.ll b/llvm/test/CodeGen/R600/xor.ll index 5a5c86d7ef5..00430417399 100644 --- a/llvm/test/CodeGen/R600/xor.ll +++ b/llvm/test/CodeGen/R600/xor.ll @@ -90,3 +90,43 @@ define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 store i32 %result, i32 addrspace(1)* %out ret void } + +; SI-CHECK-LABEL: @vector_xor_i64 +; SI-CHECK: V_XOR_B32_e32 +; SI-CHECK: V_XOR_B32_e32 +; SI-CHECK: S_ENDPGM +define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { + %a = load i64 addrspace(1)* %in0 + %b = load i64 addrspace(1)* %in1 + %result = xor i64 %a, %b + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; SI-CHECK-LABEL: @scalar_xor_i64 +; SI-CHECK: S_XOR_B64 +; SI-CHECK: S_ENDPGM +define void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { + %result = xor i64 %a, %b + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; SI-CHECK-LABEL: @scalar_not_i64 +; SI-CHECK: S_NOT_B64 +define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) { + %result = xor i64 %a, -1 + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; SI-CHECK-LABEL: @vector_not_i64 +; SI-CHECK: V_NOT_B32 +; SI-CHECK: V_NOT_B32 +define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) { + %a = load i64 addrspace(1)* %in0 + %b = load i64 addrspace(1)* %in1 + %result = xor i64 %a, -1 + store i64 %result, i64 addrspace(1)* %out + ret void +} |
