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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-24 20:08:13 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-24 20:08:13 +0000 |
| commit | 684dc80b6d0de8404d592ecaf83b0a4706366f86 (patch) | |
| tree | a0c421f34666b37a86a79183dc0118a035431170 /llvm/test/CodeGen | |
| parent | 248b7b6ba1c2a69373c9923a316baa4ed5bd19a3 (diff) | |
| download | bcm5719-llvm-684dc80b6d0de8404d592ecaf83b0a4706366f86.tar.gz bcm5719-llvm-684dc80b6d0de8404d592ecaf83b0a4706366f86.zip | |
R600/SI: Fix extra mov from legalizing 64-bit SALU ops.
Check the register class of each operand individually
to avoid an extra copy to a vgpr.
llvm-svn: 204662
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/R600/or.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/R600/or.ll b/llvm/test/CodeGen/R600/or.ll index 8e985c75cbd..be984b27122 100644 --- a/llvm/test/CodeGen/R600/or.ll +++ b/llvm/test/CodeGen/R600/or.ll @@ -89,11 +89,11 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, } ; SI-LABEL: @vector_or_i64_loadimm -; SI-DAG: S_MOV_B32 -; SI-DAG: S_MOV_B32 -; SI-DAG: BUFFER_LOAD_DWORDX2 -; SI: V_OR_B32_e32 -; SI: V_OR_B32_e32 +; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], -545810305 +; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 5231 +; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, +; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] +; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] ; SI: S_ENDPGM define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64 addrspace(1)* %a, align 8 |
