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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-25 20:21:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-25 20:21:57 +0000 |
| commit | 5d9101941f40bc23e2c1b84ce6fa444ccb0e225f (patch) | |
| tree | bb5e44506b12ecc614aad4ab730621f3da844d54 /llvm/test/CodeGen | |
| parent | bc2d34394d1ff0edbf410fbd862173c932a3cb04 (diff) | |
| download | bcm5719-llvm-5d9101941f40bc23e2c1b84ce6fa444ccb0e225f.tar.gz bcm5719-llvm-5d9101941f40bc23e2c1b84ce6fa444ccb0e225f.zip | |
AMDGPU: Set call_convention bit in kernel_code_t
According to the documentation this is supposed to be -1
if indirect calls are not supported.
llvm-svn: 293081
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hsa.ll | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/hsa.ll b/llvm/test/CodeGen/AMDGPU/hsa.ll index 12c15441c0f..972fbd66ef3 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa.ll @@ -45,6 +45,8 @@ ; HSA: .amd_kernel_code_t ; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: wavefront_size = 6 +; HSA: call_convention = -1 ; HSA: .end_amd_kernel_code_t ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 |
