[Hexagon] Properly scale bit index when extracting elements from vNi1

For example v = <2 x i1> is represented as bbbbaaaa in a predicate register,
where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4
from the predicate register.

llvm-svn: 337934

1 files changed, 18 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll b/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
new file mode 100644
index 00000000000..36c628b3594
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure that element no.1 extracted from <2 x i1> translates to extracting
+; bit no.4 from the predicate register.
+
+; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)
+; CHECK: r[[R0:[0-9]+]] = p[[P0]]
+; This is what we're really testing: the bit index of 4.
+; CHECK: p[[P0]] = tstbit(r[[R0]],#4)
+
+define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {
+  %v0 = icmp eq <2 x i32> %a0, %a1
+  %v1 = extractelement <2 x i1> %v0, i32 1
+  %v2 = zext i1 %v1 to i32
+  ret i32 %v2
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }