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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2018-12-30 07:48:09 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2018-12-30 07:48:09 +0000 |
| commit | 4aa64537676167ef3cc03cebe98c7f4d350c707c (patch) | |
| tree | d02d920caac0a698826b50b9a7a910b63bd74e85 /llvm/test/CodeGen | |
| parent | 2e8bbb9c0012246844b648edb5d3fcf5446d06d9 (diff) | |
| download | bcm5719-llvm-4aa64537676167ef3cc03cebe98c7f4d350c707c.tar.gz bcm5719-llvm-4aa64537676167ef3cc03cebe98c7f4d350c707c.zip | |
[PowerPC] Fix ADDE, SUBE do not know how to promote operator
Summary:
This patch is created to fix the Bugzilla bug 39815:
https://bugs.llvm.org/show_bug.cgi?id=39815
This patch is to support promotion integer result for the instruction ADDE, SUBE.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D56119
llvm-svn: 350161
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr39815.ll | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/pr39815.ll b/llvm/test/CodeGen/PowerPC/pr39815.ll new file mode 100644 index 00000000000..a01c8be8634 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr39815.ll @@ -0,0 +1,31 @@ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \ +; RUN: -verify-machineinstrs | FileCheck %s + +@b = common dso_local local_unnamed_addr global i64* null, align 8 +@a = common dso_local local_unnamed_addr global i8 0, align 1 + +define void @testADDEPromoteResult() { +entry: + %0 = load i64*, i64** @b, align 8 + %1 = load i64, i64* %0, align 8 + %cmp = icmp ne i64* %0, null + %conv1 = zext i1 %cmp to i64 + %add = add nsw i64 %1, %conv1 + %2 = trunc i64 %add to i8 + %conv2 = and i8 %2, 5 + store i8 %conv2, i8* @a, align 1 + ret void + +; CHECK-LABEL: @testADDEPromoteResult +; CHECK: # %bb.0: +; CHECK-DAG: addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc@ha +; CHECK-DAG: ld [[REG3:[0-9]+]], [[VAR1]]@toc@l([[REG1]]) +; CHECK-DAG: lbz [[REG4:[0-9]+]], 0([[REG3]]) +; CHECK-DAG: addic [[REG5:[0-9]+]], [[REG3]], -1 +; CHECK-DAG: extsb [[REG6:[0-9]+]], [[REG4]] +; CHECK-DAG: addze [[REG7:[0-9]+]], [[REG6]] +; CHECK-DAG: addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha +; CHECK-DAG: andi. [[REG9:[0-9]+]], [[REG7]], 5 +; CHECK-DAG: stb [[REG9]], [[VAR2]]@toc@l([[REG8]]) +; CHECK: blr +} |

