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| author | Chad Rosier <mcrosier@codeaurora.org> | 2014-06-09 01:54:00 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-06-09 01:54:00 +0000 |
| commit | 3fe0c876c427d8da80fd1bd2f94f2605fc802268 (patch) | |
| tree | 9f53ce0414531239c47cdb95417c1e6c1028d748 /llvm/test/CodeGen | |
| parent | d96e9f14ee6691236cd51a106f6a73069ee0d10e (diff) | |
| download | bcm5719-llvm-3fe0c876c427d8da80fd1bd2f94f2605fc802268.tar.gz bcm5719-llvm-3fe0c876c427d8da80fd1bd2f94f2605fc802268.zip | |
[AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037
llvm-svn: 210446
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index 97bfb5ca9d3..07373ccedc5 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -6,9 +6,10 @@ ; ; CHECK: ********** MI Scheduling ********** ; CHECK: shiftable -; CHECK: *** Final schedule for BB#0 *** -; CHECK: ADDXrr %vreg0, %vreg2 -; CHECK: ADDXrs %vreg0, %vreg2, 5 +; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 +; CHECK: Successors: +; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2 +; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2 ; CHECK: ********** INTERVALS ********** define i64 @shiftable(i64 %A, i64 %B) { %tmp0 = sub i64 %B, 20 |
