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| author | Michael Kuperstein <mkuper@google.com> | 2016-09-28 06:13:58 +0000 |
|---|---|---|
| committer | Michael Kuperstein <mkuper@google.com> | 2016-09-28 06:13:58 +0000 |
| commit | 3e06eafc2089f4c8ebca4ce632a29161d3a15df1 (patch) | |
| tree | 12b9029f88a476142ce85a4b3733690c5a4f1668 /llvm/test/CodeGen | |
| parent | 536ff0dd2f3b5c27de5c2ad0bd19ab424aae9f09 (diff) | |
| download | bcm5719-llvm-3e06eafc2089f4c8ebca4ce632a29161d3a15df1.tar.gz bcm5719-llvm-3e06eafc2089f4c8ebca4ce632a29161d3a15df1.zip | |
[DAG] Remove isVectorClearMaskLegal() check from vector_build dagcombine
This check currently doesn't seem to do anything useful on any in-tree target:
On non-x86, it always evaluates to false, so we never hit the code path that
creates the shuffle with zero.
On x86, it just forwards to isShuffleMaskLegal(), which is a reasonable thing to
query in general, but doesn't make sense if only restricted to zero blends.
Differential Revision: https://reviews.llvm.org/D24625
llvm-svn: 282567
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/r600-export-fix.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/vec-perm-13.ll | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll index 7d86f9e3b3f..665feeb678b 100644 --- a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll +++ b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll @@ -3,9 +3,9 @@ ;CHECK: EXPORT T{{[0-9]}}.XYZW ;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000 -;CHECK: EXPORT T{{[0-9]}}.0XYZ +;CHECK: EXPORT T{{[0-9]}}.0YZW ;CHECK: EXPORT T{{[0-9]}}.XYZW -;CHECK: EXPORT T{{[0-9]}}.YZ00 +;CHECK: EXPORT T{{[0-9]}}.XY00 ;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000 diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-13.ll b/llvm/test/CodeGen/SystemZ/vec-perm-13.ll index 708d8de53f8..d4aeffc6641 100644 --- a/llvm/test/CodeGen/SystemZ/vec-perm-13.ll +++ b/llvm/test/CodeGen/SystemZ/vec-perm-13.ll @@ -19,8 +19,8 @@ define <4 x i16> @f1(<4 x i16> %x) { ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .byte 6 ; CHECK-VECTOR-NEXT: .byte 7 -; CHECK-VECTOR-NEXT: .byte 16 -; CHECK-VECTOR-NEXT: .byte 17 +; CHECK-VECTOR-NEXT: .byte 22 +; CHECK-VECTOR-NEXT: .byte 23 ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .space 1 |
